EUV The Focal Point

This post was created using AI. Please check the information if you want to use it as a basis for decision-making.This week’s episode follows High-NA EUV as it moves from readiness language toward first product evidence. ASML is pointing to memory and logic products exposed within months, while imec’s quantum-dot qubit device shows how High-NA can matter beyond conventional logic and DRAM. The focus is the manufacturing loop around High-NA: masks, inspection, curvilinear data, and qualification.Key takeaways:- ASML’s CEO said first memory and logic products exposed on High-NA EUV systems should appear within months.- imec presented a quantum-dot qubit device fabricated with High-NA EUV, with barely 6-nanometer gaps between control gates.- The episode treats imec’s quantum result as a manufacturability signal, not a near-term revenue driver.- Semiconductor Engineering’s mask discussion points to inspection, repair, curvilinear qualification, and data flow as key High-NA bottlenecks.- Micron started 1-alpha DRAM manufacturing at its Manassas, Virginia fab, adding U.S. long-lifecycle memory capacity outside the EUV-heavy HBM race.- Samsung’s tentative labor deal reduced immediate strike risk, but a later court challenge kept operational uncertainty alive.- No fresh official TSMC or Rapidus update was found this week that changed the EUV outlook.- The practical High-NA question for 2026 is which product layers produce enough yield, cost, and cycle-time evidence to justify insertion.Glossary:Extreme Ultraviolet (EUV) lithography — A 13.5-nanometer exposure technology used for the most advanced semiconductor patterning layers.High Numerical Aperture (High-NA) EUV — ASML’s next EUV generation using 0.55 NA optics for finer resolution and potentially fewer patterning steps.Low Numerical Aperture (Low-NA) EUV — Today’s 0.33 NA EUV platform, still the main production workhorse at leading fabs.Dynamic random-access memory (DRAM) — Volatile memory used in servers, personal computers, mobile devices, and high-bandwidth memory stacks.High Bandwidth Memory (HBM) — Stacked DRAM used near AI accelerators to deliver very high bandwidth.Curvilinear mask — A photomask using curved rather than strictly rectangular features to improve imaging on difficult patterns.Inverse lithography technology (ILT) — Computational method that derives mask shapes from desired wafer patterns and process behavior.Actinic inspection — Mask inspection using EUV wavelength light to better determine whether a defect will print.Edge placement error — The deviation between intended and printed feature edges, increasingly important at advanced nodes.

This post was created using AI. Please check the information if you want to use it as a basis for decision-making.This week’s episode frames EUV through geography, serviceability, and industrial replication rather than a new scanner milestone. Tata Electronics and ASML put India’s first commercial 300-millimeter fab into the lithography conversation, while TSMC’s board authorizations and the MATCH Act dispute show why capacity now depends on facilities, field support, policy, and trusted regional execution.Key takeaways:- Tata Electronics and ASML signed an MoU to support the ramp of Tata’s Dholera 300-millimeter fab in Gujarat.- Tata’s disclosed Dholera portfolio spans 28nm, 40nm, 55nm, 90nm, and 110nm, making the project mainly DUV-centered rather than an EUV-frontier fab.- TSMC approved about US$31.284 billion in capital appropriations for advanced technology capacity and fab/facility systems.- TSMC also approved a capital injection of up to US$20 billion into TSMC Arizona.- Dutch objections to the proposed U.S. MATCH Act make servicing, spares, and extraterritorial export controls a live lithography-capacity issue.- China also criticized the MATCH Act, reinforcing that chip-equipment policy is becoming an operating-risk variable.- TSMC reportedly raised its 2030 global semiconductor market view to about US$1.5 trillion, with AI as the demand engine.- Apple-Intel foundry speculation is treated as background this week because the preliminary deal was already covered and no official node or product scope has changed.- No major new EUV scanner shipment or High-NA insertion datapoint was found this week, so the episode focuses on geographic replication and service infrastructure.Glossary:Extreme Ultraviolet (EUV) lithography — 13.5-nanometer wavelength lithography used for critical layers in leading-edge logic and advanced memory.Deep Ultraviolet (DUV) lithography — Earlier-generation optical lithography still essential for mature nodes and many non-critical layers in advanced flows.High Numerical Aperture (High-NA) EUV — Next-generation EUV platform with higher resolution but different economics, field-size constraints, and integration challenges.300-millimeter fab — Semiconductor wafer fab using 12-inch wafers, the standard format for high-volume modern chip manufacturing.Memorandum of Understanding (MoU) — A formal cooperation framework that may precede detailed contracts or tool orders.Capital appropriation — Board authorization to allocate capital for capacity, construction, facility systems, or related investments.Field service — Maintenance, parts, calibration, and engineering support needed to keep tools productive after installation.MATCH Act — Proposed U.S. legislation aimed at tightening semiconductor manufacturing equipment controls involving China and allied countries.Tool availability — The share of time a manufacturing tool is operational and usable for production work.

This post was created using AI. Please check the information if you want to use it as a basis for decision-making.This week’s episode looks at EUV less as a single-tool story and more as a capacity, customer, and capital-allocation story. Apple’s reported Intel and Samsung outreach, Samsung’s 2nm foundry push, SK Hynix customer-financing talks, and TSMC’s low-NA roadmap strategy all point to the same conclusion: the bottleneck is now economic and geopolitical as much as technical.Key takeaways:- Previous scripts or sources were not available in the workspace, so non-repetition was handled on a best-effort basis.- Reuters relayed a Wall Street Journal report that Apple and Intel reached a preliminary chip-making deal, but Intel and Apple declined comment and the product scope remains unclear.- Reuters also relayed Bloomberg reporting that Apple explored U.S. chipmaking with Intel and Samsung, while Reuters could not independently verify the report.- Samsung reported Q1 2026 consolidated revenue of KRW 133.9 trillion and operating profit of KRW 57.2 trillion.- Samsung said its foundry business plans full utilization of advanced-node lines in Q2 2026, broader 2nm customer engagement, and second-generation 2nm mobile ramp in H2 2026.- Reuters reported that Samsung expects more advanced 2nm logic customers and is reviewing a second Taylor, Texas fab while targeting first Taylor volume production in 2027.- Reuters reported that SK Hynix customers have proposed funding production lines and ASML EUV tools, reflecting extreme tightness in AI-driven memory supply.- TSMC introduced A13, A12, and N2U, with N2U planned for 2028 and A13/A12 planned for 2029, while continuing to extract gains from existing EUV platforms.- ASML reported Q1 2026 net sales of €8.8 billion and updated 2026 net sales guidance to €36 billion–€40 billion.- Apple A20 and C2 modem items remain rumors; they were used only as directional signals for custom-silicon and packaging demand.Glossary:Extreme Ultraviolet (EUV) — lithography using 13.5 nm light to pattern the most critical layers in advanced chips.High Numerical Aperture (High-NA) EUV — ASML’s newer 0.55 NA EUV platform designed for finer resolution and future sub-2nm logic and advanced memory.Low numerical aperture (low-NA) EUV — the 0.33 NA EUV platform widely used for current leading-edge logic and memory production.Hyper-NA — a possible future EUV generation above High-NA, still more of a 2030s feasibility topic than a near-term production tool.2nm — an advanced process-node class using nanosheet or gate-all-around transistor structures, with naming varying by foundry.Wafer-Level Multi-Chip Module (WMCM) — a packaging approach that integrates components at wafer level before singulation.High-Bandwidth Memory (HBM) — stacked DRAM used beside AI accelerators to provide very high data bandwidth.CoWoS — TSMC’s Chip-on-Wafer-on-Substrate advanced packaging family for large AI and high-performance computing packages.Backside power delivery — a routing approach that moves power delivery to the wafer backside to reduce congestion and improve performance.Foundry — a manufacturer that produces chips designed by external customers.

This post was created using AI. Please check the information if you want to use it as a basis for decision-making.Episode teaserAdvanced packaging has become one of the decisive technologies behind EUV-era semiconductors. This episode explains how modern packages connect chiplets, high-bandwidth memory, substrates, and cooling into one working system. It also maps the key players across foundries, integrated device manufacturers, OSATs, memory suppliers, substrates, materials, and equipment.Key takeaways- Advanced packaging is not EUV lithography itself. It is the system-level integration technology that makes EUV-era chips usable in real products.- A package is no longer just protection. In high-end computing, it is an electrical, thermal, mechanical, and architectural platform.- Fan-out packaging redistributes chip connections beyond the die outline using molded reconstituted wafers or panels and copper redistribution layers.- Two point five D packaging places logic and memory side by side on a high-density interposer or bridge to increase bandwidth.- Three D packaging stacks active dies vertically to shorten connections, but it makes heat removal, power delivery, testing, and yield harder.- Hybrid bonding removes conventional solder bumps and enables much denser die-to-die connections through direct copper and dielectric bonding.- High-bandwidth memory is a central driver of advanced packaging demand for AI accelerators.- TSMC, Samsung, and Intel are central high-end platform players; ASE, Amkor, and JCET are major OSAT players.- SK Hynix, Samsung, and Micron matter because advanced memory packaging is tightly linked to AI system performance.- Substrate, material, and equipment suppliers such as Ibiden, Unimicron, Shinko Electric, AT&S, Samsung Electro-Mechanics, Ajinomoto, BESI, EV Group, Applied Materials, Tokyo Electron, and ASMPT form the hidden backbone of the ecosystem.Glossary- EUV: Extreme ultraviolet lithography, a front-end chipmaking method used to print very small features in advanced semiconductor processes.- Advanced packaging: High-density semiconductor assembly and integration methods that connect multiple dies, memory stacks, substrates, and thermal structures.- Chiplet: A smaller functional die designed to be combined with other dies inside one package.- Fan-out packaging: A wafer-level or panel-level method that embeds dies and builds redistribution layers to route connections beyond the original die area.- Interposer: A high-density routing layer between dies and the package substrate, often made from silicon, organic materials, or redistribution-layer structures.- Through-silicon via: A vertical metal connection through silicon that carries signals or power between layers.- Hybrid bonding: A bonding method that joins dielectric surfaces and copper pads directly, enabling very dense vertical interconnects.- HBM: High-bandwidth memory, a stacked memory technology placed close to processors for very wide, fast data movement.- OSAT: Outsourced semiconductor assembly and test provider; a company that packages and tests chips for other semiconductor firms.- ABF substrate: A high-performance build-up substrate technology using Ajinomoto Build-up Film as an insulating material.

This post was created using AI. Please check the information if you want to use it as a basis for decision-making.This week’s episode is a light scanner-shipment week, but a strong roadmap and economics week. The central theme is coexistence: DUV, Low-NA EUV, High-NA EUV, and advanced packaging are becoming complementary tools rather than sequential replacements. The episode looks at TSMC’s A16 timing, Samsung’s record chip results, Big Tech’s AI spending pressure, and why ASML’s workhorse Low-NA fleet still matters.Key takeaways:- TSMC’s A16 is described as ready for production in 2026, but volume production is now aligned to 2027 because customer ramp timing drives the schedule.- TSMC’s A12 and A13 roadmap through 2029 continues to avoid High-NA EUV, reinforcing a strategy of extending current Low-NA EUV capability.- TrendForce frames TSMC’s High-NA deferral as a Low-NA strength story rather than a near-term collapse in EUV demand.- ASML’s near-term EUV economics remain tied to Low-NA output and upgrades, including at least 60 Low-NA EUV systems in 2026 and a path toward about 80 in 2027.- Samsung reported KRW 133.9 trillion in Q1 revenue and KRW 57.2 trillion in operating profit, with its Device Solutions division contributing KRW 53.7 trillion of operating profit.- Samsung said it started mass product sales of HBM4 and SOCAMM2 for NVIDIA’s Vera Rubin platform and plans first HBM4E samples in Q2 2026.- Reuters Breakingviews reported that Alphabet, Amazon, Meta, and Microsoft may invest up to $725 billion this year, while Alphabet said cloud revenue was limited by processor constraints.- TSMC’s SoIC roadmap points from 6-micron hybrid-bonding pitch in 2025 toward 4.5 microns in 2029, showing that packaging is increasingly part of the scaling answer.- No major new official ASML scanner shipment announcement surfaced this week; the episode therefore emphasizes roadmap timing, customer adoption, and cost-per-good-die logic.Glossary:EUV — Extreme Ultraviolet lithography, the 13.5-nanometer exposure technology used for the most critical layers in advanced chips.Low-NA EUV — Current-generation EUV lithography using a 0.33 numerical aperture optical system.High-NA EUV — Next-generation EUV lithography using a 0.55 numerical aperture system for finer patterning on selected critical layers.DUV — Deep Ultraviolet lithography, still used for many layers even in advanced chips.A16 — TSMC’s data-center-oriented node family using Super Power Rail backside power delivery.Backside power delivery — A power-routing approach that moves power rails to the back of the wafer to improve routing and power integrity.HBM4 — Fourth-generation High Bandwidth Memory for AI accelerators and high-performance computing systems.SoIC — TSMC’s System on Integrated Chips 3D stacking technology using hybrid bonding for vertical die-to-die connections.CoWoS — TSMC’s Chip on Wafer on Substrate advanced packaging platform for large AI and HPC packages.Cost per good die — The manufacturing cost of each functional die after yield, cycle time, tool cost, and process complexity are included.

This post was created using AI. Please check the information if you want to use it as a basis for decision-making.Episode teaserThis episode explains why EUV reticles are much more than chip-pattern stencils. We unpack how reflective multilayer masks work, why buried defects and mask three-dimensional effects matter, how pellicles and actinic inspection protect yield, and why reticles are central to the economics of advanced semiconductor manufacturing. We also look at what High-NA EUV changes for future reticle design, testing, and infrastructure.Key takeaways- EUV reticles are reflective multilayer optical components, not transparent masks.- The core EUV mask stack includes a low thermal expansion substrate, a molybdenum/silicon multilayer mirror, a capping layer, and a patterned absorber.- Buried multilayer defects can be printable because they can disturb the reflected EUV wavefront.- Mask three-dimensional effects arise because EUV light sees the absorber topography at an oblique angle.- Pellicles reduce particle risk, but they add EUV transmission, heating, lifetime, inspection, and cost trade-offs.- Actinic inspection uses EUV light to judge whether a mask defect is likely to print on the wafer.- Reticle economics include not only the mask itself, but also blanks, writing, inspection, repair, cleaning, pellicles, storage, and re-spin risk.- High-NA EUV makes reticle strategy more complex through anamorphic imaging, half-field exposure, possible stitching, and possible future larger mask formats.Glossary- EUV lithography: Extreme ultraviolet lithography, a chip patterning method using light near thirteen point five nanometers.- Reticle: The master mask carrying the circuit pattern for one lithography layer.- Mask blank: The unpatterned reticle substrate and optical stack before the circuit pattern is written.- Multilayer mirror: Alternating nanometer-scale layers that reflect EUV light by constructive interference.- Absorber: The patterned layer that reduces EUV reflection in dark regions of the mask.- Mask three-dimensional effects: Imaging errors caused by the real height, shape, and material properties of mask features.- Pellicle: A thin protective membrane that keeps particles away from the reticle surface.- Actinic inspection: Inspection using the same wavelength as the lithography exposure.- Aerial image review: Mask qualification that checks how a defect or repair appears under scanner-like imaging conditions.- High-NA EUV: Next-generation EUV lithography using higher numerical aperture optics for improved resolution.

This post was created using AI. Please check the information if you want to use it as a basis for decision-making.This episode looks at the split opening in advanced lithography: TSMC is extending the life of today’s EUV platform while ASML ramps Low-NA output and Intel tries to turn 14A into a real external foundry win. The focus is not whether High-NA EUV matters; it is when its cost and integration risk are justified. SK hynix’s record quarter shows why memory capacity keeps pulling on the same EUV ecosystem.Key takeaways- TSMC announced A13 for 2029 as a direct shrink of A14, with 6% area savings and full A14 design-rule compatibility.- TSMC introduced N2U for 2028, targeting 3-4% speed gains or 8-10% power reduction and 1.02-1.03X logic density over N2P.- TSMC’s 2028 14-reticle CoWoS target would combine about 10 compute dies and 20 HBM stacks, shifting more scaling value to packaging.- Tesla’s Terafab plan now names Intel 14A, making it Intel’s first major named external customer for that technology.- Intel said 14A maturity, yield, and performance are outpacing 18A at a comparable stage, while early design commitments remain expected from H2 2026 into H1 2027.- SK hynix reported KRW 52.5763T revenue, KRW 37.6103T operating profit, and a 72% operating margin in Q1 2026.- ASML says it is driving at least 60 Low-NA EUV systems in 2026 and at least 80 systems of Low-NA capacity in 2027.- No fresh material Rapidus update was found after the previously covered April 11 funding and facility announcements.GlossaryExtreme Ultraviolet (EUV) — 13.5 nm lithography used for critical layers in advanced semiconductor manufacturing.High Numerical Aperture (High-NA) EUV — Next-generation EUV with higher optical numerical aperture, improving resolution but adding cost and integration complexity.Low-NA EUV — The current production EUV platform used broadly for advanced logic and DRAM manufacturing.Chip on Wafer on Substrate (CoWoS) — TSMC advanced packaging technology that integrates large compute dies and memory stacks on an interposer/substrate.High Bandwidth Memory (HBM) — Stacked DRAM placed near accelerators to provide very high data bandwidth.Process Design Kit (PDK) — Foundry-provided design rules, device models, and verification data for a specific process.Design-Technology Co-Optimization (DTCO) — Joint optimization of chip design choices and manufacturing process constraints.Reticle — The photomask field used in lithography; reticle limits affect the maximum size of exposed dies or stitched packages.

This post was created using AI. Please check the information if you want to use it as a basis for decision-making.This week’s episode is about a subtle but important shift in EUV. ASML and TSMC did not just post strong quarters; they showed that the next constraint is usable output, not headline access to advanced lithography. We look at the new productivity data, the tighter capacity plans, and why the industry is now trying to get more wafers from the same installed base.Key takeaways:- ASML reported Q1 2026 net sales of €8.8 billion, gross margin of 53.0%, and net income of €2.8 billion.- ASML raised full-year 2026 sales guidance to €36-40 billion and kept gross-margin guidance at 51-53%.- ASML released the NXE:3800E productivity package, increasing throughput from 220 to 230 wafers per hour at similar overlay.- ASML said High-NA has processed more than 500,000 wafers and achieved more than 80% availability.- TSMC reported 1Q26 revenue of US$35.9 billion, gross margin of 66.2%, and operating margin of 58.1%.- TSMC said 7nm and below accounted for 74% of wafer revenue in 1Q26, while HPC represented 61% of revenue by platform.- TSMC lifted its 2026 revenue outlook to above 30% growth in US-dollar terms and said capex should land at the high end of US$52-56 billion.- TSMC said N2 is ramping in Hsinchu and Kaohsiung, while new N3 capacity is planned for Tainan, Arizona, and Japan through 2028.- No new official Samsung or Intel EUV disclosures materially changed the week’s core picture, so the episode centers on ASML and TSMC.Glossary:Extreme Ultraviolet (EUV) — lithography using 13.5-nanometer light for advanced chip patterning.High Numerical Aperture (High-NA) — the next EUV optical generation with higher resolution and tighter patterning capability.Wafers per hour (WPH) — a scanner throughput metric showing how many wafers a tool can expose in an hour.Overlay — how accurately one patterned layer aligns with previous layers on the wafer.Installed Base Management — service, upgrades, field options, and support revenue from already deployed tools.N2 — TSMC’s 2-nanometer-class process family, including follow-on variants such as N2P and A16.High-performance computing (HPC) — processors and accelerators for data centers, artificial intelligence, and other compute-intensive workloads.Dynamic Random-Access Memory (DRAM) — volatile memory technology used in servers, PCs, mobile devices, and High Bandwidth Memory stacks.

This post was created using AI. Please check the information if you want to use it as a basis for decision-making.This week’s episode looks at how artificial intelligence demand is feeding back into semiconductor manufacturing itself. Intel’s Terafab move, TSMC and Samsung’s new numbers, tighter equipment politics around China, and Japan’s fresh support for Rapidus all point to the same conclusion: EUV is now part of a wider manufacturing-system battle. The focus topic explains why fabs are using AI not only to sell chips, but to stabilize yield, shorten learning cycles, and make scarce lithography capacity more productive.Key takeaways- Intel formally joined Elon Musk’s Terafab effort with Tesla and SpaceX, turning a previously speculative foundry link into an announced partnership.- The proposed U.S. MATCH Act would extend pressure from already-banned EUV exports to DUV equipment sales and servicing, making support capacity itself a policy lever.- TSMC reported March 2026 revenue of NT$415.19 billion and first-quarter revenue of NT$1.134 trillion, up 35.1% year over year.- Samsung guided first-quarter 2026 sales of about 133 trillion won and operating profit of about 57.2 trillion won.- Samsung says it is feeding wafer-level pattern data back into design, using agentic AI for diagnostics, and running a Pyeongtaek fab digital twin on NVIDIA Omniverse.- Gartner forecasts 2026 semiconductor revenue at $1.3202 trillion, with memory revenue at $633.3 billion and meaningful pricing relief not expected until late 2027.- Japan approved another 631.5 billion yen for Rapidus, while Rapidus also announced NEDO approval for its FY2026 plan and opened new analysis and chiplet facilities.- One relevant thread remains unclear: Samsung’s reported 1 nm forksheet roadmap is still unofficial and should be treated as directional rather than confirmed.GlossaryEUV — Extreme Ultraviolet lithography used for the most advanced patterning layers in semiconductor manufacturing.DUV — Deep Ultraviolet lithography, an older but still strategically important class of patterning tools.High-NA — High Numerical Aperture EUV, the next EUV platform aimed at higher resolution and fewer multi-patterning steps on critical layers.HBM — High Bandwidth Memory, a stacked memory architecture used heavily in AI accelerators.HBM4E — An expected enhanced generation of HBM4 with tighter quality and yield requirements for advanced memory production.Digital twin — A software-based virtual replica of a fab or process used for monitoring, simulation, and risk reduction.MES — Manufacturing Execution System software that tracks and coordinates production on the fab floor.PDK — Process Design Kit, the rule set and models chip designers need to design for a specific manufacturing process.Chiplet — A smaller die designed to be combined with other dies in an advanced package rather than built as one large monolithic chip.TAT — Turnaround Time, the elapsed time needed to move a design or wafer flow through a development or production cycle.

This post was created using AI. Please check the information if you want to use it as a basis for decision-making.Episode teaserMoore’s law is usually described as a promise that chips keep getting faster. This episode makes the case that the original idea was really an economic observation about how dense, useful circuitry could become cheaper to manufacture over time. We trace that story from the integrated circuit and the Intel 4004 through the Pentium, Apple’s M1, EUV lithography, and the modern AI accelerator era.Key takeaways- Moore’s law started as an economics-of-manufacturing idea, not a law of physics.- Its success depended on rising density, improving yields, larger wafers, and smarter circuit design.- Famous chips like the Intel 4004, 8086, and Pentium marked different commercial stages of the curve.- The end of easy voltage scaling broke the old link between more transistors and automatic clock-speed gains.- Modern progress increasingly comes from system integration, packaging, and workload-specific specialization.- EUV lithography helped extend advanced-node scaling, but it did not erase cost and yield trade-offs.- AI is now both a demand engine and a design target for the semiconductor roadmap.- The future of Moore’s law is broader and messier: less about one clean density curve, and more about useful computing per dollar and per watt.Glossary- Moore’s law — The long-run trend that economically useful chip complexity rises roughly exponentially over time.- Integrated circuit — A device that places many electronic components on one piece of semiconductor material.- Yield — The share of manufactured chips that work correctly and can be sold.- x86 — A processor family that became dominant in personal computers and many servers.- System on a chip — A chip that combines multiple major functions in one integrated design.- EUV lithography — A chip-patterning method that uses extremely short-wavelength light to print advanced features.- Chiplet — A smaller die designed to be combined with others inside one package.- Domain-specific accelerator — A processor block optimized for a particular workload, such as AI matrix operations.

This post was created using AI. Please check the information if you want to use it as a basis for decision-making.This week’s episode argues that EUV is becoming less of a pure lithography story and more of an infrastructure story. The most useful signals are commercial productization at Intel, long-duration power procurement at ASML, larger geographic ambition around TSMC, and policy moves that could affect the usable life of installed tools. It was a relatively light week for fresh scanner disclosures, so the emphasis is on economics, contracts, and industrial positioning.Key takeaways- Intel said its Core Ultra Series 3 with vPro is the first commercial PC platform built on Intel 18A, covering more than 125 business designs.- RWE expanded and extended its renewable power agreement with ASML to 130 megawatts through 2038.- The reported plan for TSMC to build 12 fabs, four packaging facilities, and an R&D center in Arizona remains unconfirmed and should be treated as rumor, not company guidance.- Reuters reported that proposed U.S. legislation would not only restrict certain chipmaking equipment sales to China but also halt servicing for named Chinese chipmakers.- SK hynix’s disclosed order for about 11.95 trillion won of ASML tools remains one of the clearest signs that memory makers are reserving future lithography capacity early.- Broadcom said TSMC capacity is a bottleneck in 2026 and that customers are increasingly signing multi-year supply agreements.- Broadcom’s new long-term deal to develop Google’s custom AI chips through 2031 shows that end-market demand is becoming more contractual and longer dated.- ASML said in its 2025 annual report that EUV revenue should increase significantly in 2026 because of advanced logic and DRAM demand.- This was a lighter week for brand-new EUV tool announcements, so some near-term uncertainty remains around exact fab and tool timelines.GlossaryExtreme Ultraviolet (EUV) — Lithography that uses 13.5-nanometer light for the most advanced chip patterning.Deep Ultraviolet (DUV) — Older lithography technology that still handles a large share of commercial chip production.High Bandwidth Memory (HBM) — Stacked memory used heavily in artificial-intelligence accelerators and servers.Power Purchase Agreement (PPA) — A long-term contract to buy electricity at agreed terms.Advanced packaging — Methods that connect multiple chiplets or dies into one high-performance package.Installed base — The tools already operating at customer sites and generating output and service revenue.18A — Intel’s leading-edge process generation now moving from launch claims into commercial products.Dynamic Random-Access Memory (DRAM) — Mainstream working memory used in servers, personal computers, and many other systems.

This post was created using AI. Please check the information if you want to use it as a basis for decision-making.This week’s episode is a light-week update that focuses on what the newest factory and financing signals say about Extreme Ultraviolet lithography. The key story is not a dramatic new scanner milestone, but the spread of EUV into more geographies, more product classes, and more pre-committed capital. TSMC’s Japan approval, Intel’s commercial 18A launch, and SK hynix’s financing move all point in the same direction: EUV is becoming an operational replication problem.Key takeaways- Taiwan approved TSMC’s plan to bring 3nm production to its second Kumamoto fab, with equipment installation and mass production targeted for 2028.- Local reporting tied the approved Kumamoto 3nm plan to roughly 15,000 12-inch wafers per month of capacity.- Intel said Core Ultra Series 3 with vPro is the first commercial PC platform built on Intel 18A and is expected to support more than 125 designs.- SK hynix made a confidential filing for a U.S. listing that could raise roughly $9.6 billion to $14.4 billion, adding a financing angle to its recent EUV capacity push.- ASML said in its 2025 annual report that it expects EUV revenue to increase significantly in 2026 because of advanced logic and DRAM demand.- This was a light week for fresh EUV datapoints: there were no major new official High-NA yield, uptime, or shipment disclosures from ASML, Samsung, Micron, or Rapidus in the last seven days.GlossaryExtreme Ultraviolet (EUV) lithography — A chip-patterning technology that uses 13.5-nanometer light for advanced semiconductor layers.High Numerical Aperture (High-NA) EUV — The next EUV platform generation, using a larger numerical aperture to improve resolution.3nm — A leading-edge logic process class that uses EUV on critical layers, despite the name not matching a literal feature size.Intel 18A — Intel’s angstrom-era manufacturing node, using RibbonFET transistors and backside power delivery.Dynamic Random-Access Memory (DRAM) — Mainstream volatile memory used in servers, PCs, mobile devices, and as the base technology for HBM stacks.High Bandwidth Memory (HBM) — Stacked memory designed to feed very high data rates to artificial intelligence and high-performance accelerators.12-inch wafer — The 300-millimeter silicon wafer format used for modern high-volume advanced chip production.

This post was created using AI. Please check the information if you want to use it as a basis for decision-making.This week’s episode looks at how EUV demand is turning into explicit capital commitments instead of general roadmap talk. The headline items are SK hynix’s nearly $8 billion scanner order, imec’s High-NA EUV installation in Leuven, and the way AI memory and foundry partnerships are starting to reshape lithography demand. The bigger point is that the scarce resource is no longer just the machine. It is early access to the whole learning curve around the machine.Key takeaways- SK hynix disclosed a 11.95 trillion won purchase of EUV scanners from ASML Korea, with completion scheduled by December 31, 2027.- imec received an ASML EXE:5200 High-NA EUV system in Leuven and expects full qualification by Q4 2026.- The imec tool will support the NanoIC pilot line and gives ecosystem partners shared access to early High-NA process learning.- Samsung and AMD said they will align on primary HBM4 supply for AMD’s Instinct MI455X and also discuss a future foundry partnership.- Micron raised fiscal 2026 capital spending plans by $5 billion to more than $25 billion, with more increases expected in 2027.- Micron has started retrofitting the Tongluo P5 site in Taiwan, plans a second cleanroom there by the end of fiscal 2026, and expects meaningful shipments from the existing fab in fiscal 2028.- Broadcom said TSMC capacity is becoming a bottleneck into 2027, reinforcing the case for earlier capacity reservation across the AI supply chain.- Europe’s EUV leverage remains system-level: scanner integration, optics, source technology, and shared pilot-line process development.GlossaryExtreme Ultraviolet (EUV) lithography — Chip patterning technology that uses 13.5-nanometer light to print very small features.High Numerical Aperture (High-NA) EUV — The next EUV generation with higher optical numerical aperture for tighter patterning and fewer multi-patterning steps.EXE:5200 — ASML’s High-NA EUV platform now being installed at selected early-access sites.High Bandwidth Memory 4 (HBM4) — A stacked memory generation designed for AI accelerators that need very high bandwidth and power efficiency.Pilot line — A shared development environment used to validate processes, materials, and integration before high-volume production.Cost per wafer — The effective manufacturing cost of processing one wafer, influenced by tool throughput, uptime, yield, and process complexity.Overlay — The accuracy with which one lithography layer is aligned to previous layers on the wafer.Laser-produced plasma (LPP) source — The EUV light source method in which lasers hit tin droplets to generate 13.5-nanometer radiation.

This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.EUV lithography isn’t just a machine purchase. It’s an ecosystem-scale coordination problem with a balance sheet attached. This episode explains “coordinated manufacturability” in EUV terms: how chipmakers line up design, masks, materials, metrology, facilities, software, and service so that a quarter‑billion‑dollar bottleneck actually produces shippable chips.KEY TAKEAWAYS- EUV economics are dominated by fixed costs. The payback comes from sustained utilization, yield, and fast learning cycles.- A modern EUV scanner is priced in the hundreds of millions of dollars, and High‑NA tools are around $400 million each.- The “EUV bill” includes far more than scanners: masks, inspection, materials, fab utilities, and data infrastructure can bottleneck output.- Throughput and uptime are the biggest economic sensitivities in cost-of-ownership models.- Service, spares, and field upgrades are part of the EUV platform strategy, not an afterthought.- Faster cycle time accelerates learning. Learning speed is an economic variable, not just an engineering one.- Shared pilot lines and consortia reduce duplicated early learning and speed up ramps when frontier development costs explode.- Energy per wafer pass is now tracked as a performance metric, because utilities and cleanroom capacity can become limiting constraints.GLOSSARY- Coordinated manufacturability: Managing design and manufacturing as one economic system so bottlenecks don’t strand capital.- Cost of ownership (CoO): A framework that totals capital and operating costs per unit of useful output, sensitive to throughput and uptime.- Cost of technology: Industry shorthand for the total cost to produce a given generation of chips at target performance and yield.- Installed base management: Service, spares, upgrades, and support revenue tied to the installed fleet of lithography tools.- Field upgrade: A post-installation hardware/software upgrade that increases productivity or capability of an existing tool.- Mask set: The full collection of photomasks required to pattern a chip’s layers; a significant NRE (non-recurring engineering) cost.- Pilot line: A shared or dedicated facility for prototyping and de-risking process steps before mass production.- Uptime / availability: The fraction of time a tool is ready for productive operation; a key driver of effective capacity.

This post was created using AI. Please check the information if you want to use it as a basis for decision-making.High-NA EUV moved closer to factory reality this week, but the bigger story is that AI demand is now reshaping the whole manufacturing stack around it. ASML supplied new readiness numbers, NVIDIA showed how AI is moving into lithography and verification flows, and Micron, SK hynix and Applied Materials made fresh moves around HBM, wafers and capacity. This episode explains why the competition is shifting from isolated tool milestones to coordinated manufacturability.Key takeaways- ASML said its High-NA EUV tools have processed about 500,000 wafers, are running at roughly 80% uptime, and target 90% uptime by the end of 2026.- NVIDIA said Samsung, SK hynix and TSMC are using GPU-accelerated software for semiconductor design and manufacturing; Samsung and SK hynix were specifically named in computational lithography and physical verification.- Micron said its 36GB 12H HBM4 is in high-volume production for NVIDIA Vera Rubin, with more than 2.8 TB/s bandwidth and about 20% better power efficiency.- Micron completed the acquisition of PSMC’s Tongluo P5 site in Taiwan and plans to retrofit the existing cleanroom now, with a second similar-sized cleanroom planned by the end of fiscal 2026.- Applied Materials said Micron and SK hynix will be founding partners at its EPIC Center, a planned $5 billion semiconductor equipment R&D effort.- SK Group Chairman Chey Tae-won said AI-driven wafer shortages could continue until 2030 and remain above 20% because HBM consumes large amounts of wafer capacity.- TSMC reported January-February 2026 revenue of NT$718.91 billion, up 29.9% year over year.- Public reporting still lacks customer-by-customer High-NA insertion dates, layer choices and product-specific deployment schedules.GlossaryExtreme Ultraviolet (EUV) lithography — Advanced chip-patterning technology using 13.5 nm light for leading-edge semiconductor manufacturing.High Numerical Aperture (High-NA) EUV — The next EUV platform generation aimed at reducing process complexity and improving patterning economics at future nodes.High Bandwidth Memory (HBM) — Stacked DRAM used near AI accelerators to deliver very high memory bandwidth.HBM4 — The next major HBM generation, positioned for AI platforms such as NVIDIA Vera Rubin.Dynamic Random Access Memory (DRAM) — Mainstream volatile memory used in servers, PCs, mobile devices and the base dies behind HBM.Computational lithography — Software-intensive correction and optimization used to make mask patterns print accurately on wafers.Physical verification — Design checks that confirm a chip layout can be manufactured reliably under process rules.Advanced packaging — Technologies that connect or stack multiple chips closely to improve bandwidth, power and system performance.Uptime — The share of time a tool is available and operating as intended in a manufacturing environment.Cleanroom — A tightly controlled fabrication space designed to minimize particles, contamination and process variation.

This post was created using AI. Please check the information if you want to use it as a basis for decision-making.This week’s episode is a lighter but more revealing EUV week. The headlines are less about splashy new product launches and more about whether High-NA EUV, sub-2 nm patterning, and 2 nm capacity plans are becoming operationally credible. The through-line is simple: the bottleneck is moving from physics toward execution, cost, and integration.Key takeaways:- ASML says its High-NA EUV tools are ready for serious high-volume production insertion after processing about 500,000 wafers, with roughly 80% uptime today and a 90% year-end target.- Intel is rethinking whether 18A should be offered more broadly to outside foundry customers, which could change future EUV tool loading and customer qualification plans.- Rapidus raised ¥267.6 billion, including ¥100 billion from Japan’s IPA and ¥167.6 billion from 32 private-sector companies, to support 2 nm mass production plans for 2027.- Chinese semiconductor executives are openly calling for a national lithography push during 2026–2030, underscoring that lithography remains a system-level bottleneck.- IBM’s SPIE 2026 roadmap argues that below-2 nm progress depends on edge placement error, stochastic control, resist and mask behavior, and integration economics, not just raw resolution.- The economic case for High-NA improves only if it removes multiple low-NA steps without losing uptime, yield, or integration margin.- Advanced packaging, reticle stitching, and back-end alignment are becoming more central to EUV value as AI chip architectures get more complex.- In a light-news week, the clearest competitive signal is who reduced uncertainty with official numbers and manufacturable process data.Glossary:Extreme Ultraviolet (EUV) lithography — A chip-patterning method that uses 13.5 nm light to print the smallest and most critical features.High Numerical Aperture (High-NA) EUV — The next EUV platform generation, using 0.55 numerical aperture optics for higher resolution and fewer patterning steps at advanced nodes.Edge placement error (EPE) — The difference between the intended feature edge location and the printed result on the wafer.Stochastic defects — Random patterning failures caused by the probabilistic nature of photons, resist chemistry, and small feature dimensions.k1 factor — A lithography scaling parameter used to describe how aggressively an optical system is being pushed toward its resolution limit.Metal-oxide resist (MOR) — A photoresist class used in advanced EUV patterning, valued for resolution, roughness, and thin-film performance.18A — Intel’s advanced process node, relevant here because broader foundry use would affect future EUV demand and capacity planning.Reticle stitching — A method of joining adjacent exposure fields or patterned regions, often relevant for large-field packaging and advanced integration schemes.

This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.EUV scanners get the spotlight, but the wafer is the precision “canvas” that makes EUV possible. In this episode we trace how a silicon wafer is made—from ultra-pure polysilicon, to a single-crystal ingot, to slicing, polishing, and atomic-level cleaning—and then connect those steps to EUV’s brutal focus and defectivity budgets.Key takeaways- Wafers start from ultra-pure polysilicon, then become single-crystal ingots typically grown by the Czochralski method.- The ingot is sliced into wafers, commonly using multi-wire sawing, followed by edge rounding, flattening, etching, and CMP polishing.- “Flatness” has multiple scales: global thickness variation (micrometers), warp (tens of micrometers), site flatness (tens of nanometers), and nanotopography (single-digit nanometers).- EUV’s limited depth of focus turns nanometer-scale height variation into printed CD and yield problems.- Cleanliness is not just “low particles”; it includes trace metal contamination limits expressed in atoms per square centimeter.- Wafer manufacturing is capital intensive and geographically concentrated among a small set of suppliers with sites across Asia, Europe, and the USA.Glossary- Wafer: A thin slice of single-crystal semiconductor that serves as the substrate for making integrated circuits.- Czochralski method (CZ): Crystal growth method that pulls and rotates a seed crystal from molten silicon to form a cylindrical single-crystal ingot.- MCz (Magnetic Czochralski): CZ growth with an applied magnetic field to control melt flow and improve uniformity.- CMP (Chemical Mechanical Polishing): Combined chemical and abrasive polishing that produces a highly planar, mirror-finish wafer surface.- GBIR / TTV: Global thickness variation metric describing overall wafer thickness non-uniformity.- Warp / Bow: Measures of wafer out-of-plane deformation; important for handling and chucking.- SFQR: A site flatness metric used to quantify flatness over defined local areas relevant to lithography fields.- Nanotopography: Low-amplitude surface height variations over millimeter-scale windows that can drive focus fingerprints.- TXRF / ICP-MS / SIMS: Analytical methods used to measure trace elemental contamination on wafer surfaces.- FOUP: Front Opening Unified Pod; standardized wafer carrier used in fabs.

This post was created using AI. Please check the information if you want to use it as a basis for decision-making.This week’s episode is about EUV productivity: ASML’s kilowatt-class source milestone, and the process-side levers that can help turn more photons into more wafers. We also look at why AI-driven demand keeps EUV on the critical path, and how ASML is positioning “beyond EUV” for chiplet-era integration.Key takeaways- ASML says it has demonstrated a 1,000-watt EUV source under customer-representative requirements, up from roughly 600 watts today.- ASML links higher source power to a productivity path from ~220 wafers per hour today to ~330 wafers per hour by 2030.- ASML technologists described a roadmap path beyond 1,000 watts, citing ~1,500 watts as “clear” and “no fundamental reason” not to reach 2,000 watts.- imec reports a 15–20% faster photo-speed for metal-oxide resists when oxygen during post-exposure bake rises from 21% to 50%, enabling dose reduction.- Dose reduction and source-power scaling are complementary levers: fabs can spend gains on higher throughput or on yield/process margin.- ASML’s 2025 annual report reports €32.7bn net sales, 52.8% gross margin, €4.7bn R&D spend, and 48 EUV systems sold (out of 535 total systems).- ASML told Reuters it is expanding its portfolio “beyond EUV,” including interest in advanced packaging, 3D integration tooling, and potentially larger chip printing.- Meta’s multi-year agreement with AMD, framed at up to 6GW of AMD Instinct GPUs, illustrates how hyperscaler AI buildouts can keep pressure on leading-edge and memory capacity.GlossaryExtreme Ultraviolet (EUV) — 13.5 nm lithography used for the most advanced chip patterning.Wafers per hour (WPH) — a scanner throughput metric describing processed wafers per hour.Laser-produced plasma (LPP) — EUV light generation method using a laser to create plasma from tin droplets.Carbon dioxide (CO₂) laser — high-power laser used in EUV source systems to drive the plasma.Post-exposure bake (PEB) — thermal step after exposure that influences resist chemistry and final dimensions.Metal-oxide resist (MOR) — EUV photoresist class often used for high-resolution, low-roughness patterning.Pellicle — thin membrane protecting the photomask from contamination during exposure.Advanced packaging — technologies that connect multiple dies (chiplets) via high-density bonding/interconnect.Exposure dose — energy delivered to the resist; lower dose can improve throughput if other limits allow.

Disclaimer: This post was created using AI. Please check the information if you want to use it as a basis for decision-making.This week’s episode tracks a split-cycle semiconductor economy: AI infrastructure keeps pulling leading-edge capacity forward, while consumer hardware feels unusually quiet. We look at what that means for Extreme Ultraviolet lithography decisions, from export-control pressure to new fab ramp plans. The common thread is allocation—of tools, service capacity, and calendar certainty.Key takeaways:- U.S. lawmakers are pushing for tighter, countrywide export controls on chipmaking tools to China, including attention to servicing and subcomponents.- For EUV-heavy fabs, restrictions on spares and service can translate directly into effective capacity, not just future shipment limits.- Rapidus’ business plan targets 2nm-class production in fiscal 2027 H2 and a ramp toward ~25,000 wafer starts per month within the first year.- Rapidus says it must install and calibrate 200+ tools before yield stabilization—an execution test as much as a technology test.- TrendForce cites a 2027–2028 window for High-NA EUV mass-production use, framing near-term planning without changing 2026 constraints.- Tom’s Hardware argues AI infrastructure spending is reshaping consumer electronics, with pricing pressure and fewer “headline” launches.- The episode’s focus: EUV is the allocation mechanism for the leading edge, and the “average product mix” assumption is breaking.- Outlook watch: export-control rules on servicing, Rapidus milestone cadence, and whether consumer component pricing finds a new equilibrium.Glossary:- Extreme Ultraviolet (EUV) lithography — 13.5 nm lithography used for advanced semiconductor patterning.- High Numerical Aperture (High-NA) EUV — Next-generation EUV tools with higher NA for improved resolution.- Wafer starts per month — A fab capacity metric describing how many wafers begin processing each month.- Wafer fab equipment (WFE) — The toolset used to manufacture semiconductor wafers (lithography, etch, deposition, metrology, etc.).- Semiconductor manufacturing equipment (SME) — A broader term often used in policy contexts for chipmaking tools and key subcomponents.- High-bandwidth memory (HBM) — Stacked DRAM designed for very high throughput, commonly paired with AI accelerators.- Double data rate fifth generation (DDR5) — Mainstream DRAM interface standard used in PCs and servers.- Yield stabilization — The phase where a new process reaches repeatable, economical defect and performance levels.

This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.Logic chips think, graphics chips see, memory chips remember—but under the hood, they’re all transistors optimized for different constraints.In this episode we compare CPUs/SoCs, GPUs, and modern memory (SRAM, DRAM, NAND) through the lens of the EUV era: what the finished chips look like, what they’re used for, and why scaling shifts bottlenecks toward data movement and packaging.Key takeaways- “Logic” chips are dominated by wiring, power, and variability management—not just transistor switching speed.- CPUs optimize for latency and control; GPUs optimize for throughput and sustained data-parallel work.- SRAM is fast and refresh-free but expensive per bit, so it lives on logic dies as caches and registers.- DRAM is far denser but needs refresh, so it becomes main memory and the stacked memory used in HBM.- NAND flash is non-volatile storage that trades write/erase complexity and wear for ultra-low cost per bit.- EUV shows up in finished logic chips as higher density, enabling more compute, more cache, and more specialized accelerators.- EUV shows up in advanced DRAM as continued scaling, more bits per wafer, and improved power efficiency.- As compute gets denser, performance increasingly depends on moving data efficiently—making memory technology and packaging central.- HBM uses a wide, short-reach interface near the logic die to deliver extreme bandwidth with better energy per bit than long, high-speed board links.Glossary- Logic chip: A chip whose primary job is computation and control (CPUs, SoCs, accelerators).- GPU (graphics processing unit): A throughput-oriented logic chip built from many parallel compute blocks.- SRAM (static random access memory): Fast volatile memory built from bistable circuits; used mainly for on-chip cache.- DRAM (dynamic random access memory): Dense volatile memory that stores bits as charge and requires refresh.- NAND flash: Non-volatile memory used for storage; retains data without power by trapping charge.- GDDR: Graphics DRAM family commonly used as external memory on GPU add-in boards.- HBM (high bandwidth memory): 3D-stacked DRAM placed close to a logic die to provide very high bandwidth.- Chiplet: A design style that splits a system into multiple dies connected by high-speed package links.- Advanced packaging: Packaging technologies that integrate multiple dies closely (e.g., interposers and dense die-to-die links).

*This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.*This week, Europe turns High-NA EUV from a roadmap slide into shared infrastructure as imec inaugurates NanoIC in Leuven. At the same time, Samsung switches from sampling to shipping HBM4, and capital plans from TSMC and Micron underline how tightly advanced nodes, packaging, and memory are now coupled. We close with a procurement reality check: when scarcity spreads beyond scanners, trust becomes an engineering variable.Key takeaways:- NanoIC launched at imec as Europe’s largest Chips Act pilot line, with a 2.5B euro investment package and major EU and national funding.- imec expects its first High-NA lithography tool to arrive in mid-March 2026, with reporting pointing to March 18.- NanoIC is positioned as an “EUV-ready” design-to-process loop, emphasizing PDKs, mask/data preparation, inspection, and defect learning speed.- Samsung says it has started shipping HBM4 to customers, claiming 11.7 Gbps consistent speed and a path to 13 Gbps.- HBM4 ramps translate into EUV load: more critical exposures, masks, resists, and metrology cycles needed to keep DRAM yields stable.- TSMC approved about $44.962B in capital appropriations spanning advanced technology, advanced packaging, and fab construction systems.- Micron’s New York megafab project progressed through January milestones, framed as a multi-decade, multi-fab domestic memory capacity hedge.- Claus Aasholm argues “trust, but verify” and supplier transparency matter most when leverage shifts during tight cycles.- Unclear: Samsung did not name HBM4 customers, and shipment volumes and yield trajectories were not disclosed.Glossary:EUV — Extreme Ultraviolet lithography using 13.5 nm light for advanced patterning.High-NA — High numerical aperture EUV optics (NA ~0.55) enabling higher resolution but new field/mask trade-offs.Numerical aperture (NA) — Optical parameter describing how much light an imaging system can accept; higher NA improves resolution.HBM4 — Sixth-generation high-bandwidth memory stack used near AI accelerators for very high throughput.PDK — Process Design Kit; a foundry/R&D-provided bundle of rules, models, and libraries for chip design.OPC — Optical Proximity Correction; computational steps that pre-distort mask patterns to print correctly on wafer.Pellicle — Thin membrane protecting EUV masks from particles, trading transmission for defect reduction.Defectivity — Rate and types of defects introduced during processing that impact yield and reliability.Digital twin — High-fidelity simulation model of a fab or tool used for optimization and predictive maintenance.

This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.ASML’s latest results show EUV bookings still dominate the conversation, while High-NA starts to surface in routine reporting. ZEISS is pushing actinic mask qualification throughput with AIMS EUV 3.0, and TSMC’s Japan plan signals that leading-edge EUV operations may spread further. This week’s theme is simple: the fastest feedback loop wins.Key takeaways:- ASML reported Q4 2025 net bookings of €13.2B, including €7.4B in EUV, and said it recognized revenue for two High-NA systems.- ASML guided 2026 total net sales to €34–39B, signaling sustained tool demand.- ASML said it will streamline Technology and IT; Reuters reported the plan could involve about 1,700 job cuts.- ZEISS said AIMS EUV 3.0 is being deployed globally and delivers triple mask throughput versus the prior generation.- ZEISS highlighted Digital FlexIllu to emulate scanner illumination for both low-NA EUV and High-NA workflows on one system.- Reuters reported TSMC plans to mass-produce 3nm chips in Kumamoto, Japan; local media cited ~$17B investment while TSMC did not confirm the figure.- Be cautious with AI-generated investor commentary around Japan’s chip push; verify claims against primary statements and major wires.- Imec’s NanoIC pilot line released A14 logic and eDRAM pathfinding PDKs to support earlier design-technology co-optimization beyond 2nm.- MarketsandMarkets (via PR Newswire) forecast EUV lithography growing from $15.84B (2026) to $30.36B by 2032.- Unclear/publicly limited: customer-by-customer High-NA ramp schedules and mask defect printability budgets remain mostly non-disclosed.Glossary:EUV lithography — Extreme Ultraviolet lithography using ~13.5 nm light to pattern advanced semiconductor features.High-NA — High numerical aperture EUV (0.55 NA class) enabling higher resolution than 0.33 NA EUV systems.Numerical aperture — Optical parameter that sets resolution and depth of focus; higher NA increases resolution but tightens process margins.Actinic mask qualification — Mask inspection/verification at the exposure wavelength regime to assess defect printability under scanner-like conditions.AIMS — Aerial Image Measurement System; actinic tool used to evaluate EUV mask defect printability and scanner matching.Scanner matching — Aligning mask qualification conditions with scanner optics and illumination to predict wafer printing behavior.Illumination — The spatial/angular distribution of light used in exposure; affects imaging, process window, and defect printability.Overlay — Alignment accuracy between patterned layers; becomes more difficult as pitches shrink and depth of focus narrows.PDK — Process Design Kit; a set of design rules, device models, and flows enabling chip design for a given process technology.Design-technology co-optimization — Joint optimization of design rules, layouts, and process integration to reduce risk and improve manufacturability.

Modern chips are no longer “just smaller.” They’re built as 3D systems: memory stacked on logic, multiple chiplets stitched together in advanced packages, power delivered through the backside of the wafer, and—sometimes—data moved with light instead of copper. This episode tours the core technologies reshaping how high-performance processors are designed and manufactured.KEY TAKEAWAYS- HBM boosts bandwidth by stacking DRAM and using a very wide, short electrical interface near the compute die.- Next-gen GDDR boosts bandwidth by pushing much higher per-pin signaling over longer board traces, trading cost for harder signal integrity.- Advanced packaging has become part of architecture: interposers, bridges, fan-out, and true 3D stacking are performance tools now.- Chiplets improve yield and modularity, but shift the bottleneck to die-to-die interconnect and package-level thermal design.- Backside power delivery separates power routing from signal routing to relieve congestion and improve power integrity—at the cost of process complexity.- Gate-all-around nanosheets improve electrostatic control beyond FinFETs, enabling further logic scaling.- 2D materials like MoS2 and WSe2 look promising as ultra-thin channels, but manufacturable integration is still a major hurdle.- Optical interconnects and silicon photonics can cut the pain of long, high-bandwidth copper links, but electrical–optical conversion and packaging are the “optics tax.”GLOSSARY- HBM (High Bandwidth Memory): 3D-stacked DRAM with a very wide interface for high bandwidth and good energy efficiency.- GDDR: High-speed graphics DRAM used on PCBs; bandwidth scales mainly by higher per-pin data rates.- TSV (Through-Silicon Via): Vertical conductor through a die, enabling dense 3D connections in stacked devices.- 2.5D Packaging: Side-by-side dies connected by an interposer or bridge that provides very dense routing.- 3D Stacking: Vertical die integration; can be memory-on-logic or logic-on-logic.- Hybrid Bonding: Direct copper-to-copper (and oxide-to-oxide) bonding for very fine-pitch vertical interconnects.- Chiplet: A modular die used as a building block in a larger package-level system.- Backside Power Delivery: Power routing moved to the wafer backside to improve power integrity and free front-side routing resources.- GAA (Gate-All-Around): Transistor architecture where the gate surrounds the channel for strong electrostatic control.- Silicon Photonics: Optical components integrated with silicon manufacturing to enable high-bandwidth optical links near chips.This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

ASML’s Q4 2025 results turned the A.I. chip boom into a lithography backlog that looks more like a capacity reservation system than a sales pipeline. This week we connect that record order intake to the real factory constraint: usable exposures per day in Extreme Ultraviolet. Then we zoom out to the “memory wall” and why high-bandwidth memory demand feeds directly into E. U. V. tool time.Key takeaways:- ASML ended 2025 with a €38.8B backlog, and Q4 net bookings of €13.2B included €7.4B of E. U. V. systems.- ASML guided 2026 net sales to €34–39B with gross margin of 51–53%, signaling execution and fab readiness as key limiters.- A new ASML share buyback program of up to €12B through 2028 underscores confidence in multi-year demand visibility.- The “memory wall” is shifting system performance bottlenecks from compute to bandwidth and data movement, accelerating demand for HBM and server DRAM.- Rising HBM demand tends to increase E. U. V. intensity in advanced DRAM as pitches shrink and multi-patterning becomes less tolerable.- High-N. A. E. U. V. is moving from prototype to factory accountability, with ASML recognizing revenue for two High-N. A. systems in Q4.- In the A.I. era, the strategic variable is not just tool count but throughput, defectivity, and cycle time at the E. U. V. bottleneck.- Missing/unclear: Several major E. U. V. buyers have provided limited new, on-the-record near-term installation and ramp timelines beyond recent earnings disclosures.Glossary:Backlog — Accumulated value of accepted system orders not yet recognized as revenue.Net bookings — Order intake for systems (and related adjustments) accepted during a period.Extreme Ultraviolet (E. U. V.) lithography — 13.5 nm wavelength lithography used for leading-edge patterning.High numerical aperture (High-N. A.) — Higher-NA E. U. V. optics aimed at improved resolution and reduced multi-patterning.Throughput — Productive wafers per hour/day; the practical capacity metric at bottleneck tools.Stochastic variability — Random process noise that can cause line-edge roughness, defects, or yield loss at small features.Multi-patterning — Using multiple exposures/etch steps to achieve smaller pitch than a single lithography step can print.HBM — High-bandwidth memory, typically stacked DRAM used with accelerators to increase memory bandwidth.DDR5 — A mainstream server memory generation whose demand rises with inference-scale deployments.Installed base management — Service, options, and support revenue tied to the fleet of deployed tools.This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

EUV lithography is governed by operational currencies.From wafers per hour to stochastic defect rates and downtime cost, these KPIs define what is technically possible and economically viable.This episode decodes the most important EUV-relevant metrics and their trade-offs.Key Takeaways- WPH reflects physics, chemistry, and system efficiency- Availability often matters more than peak throughput- EUV yield is limited by stochastic effects- Dose links pattern quality to productivity- Downtime cost strongly shapes EUV economicsGlossaryWPH: Wafers processed per hourOEE: Overall equipment effectivenessOverlay: Layer-to-layer alignment accuracyDOF: Depth of focus toleranceCOO: Cost of ownershipThis article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

This week, the EUV story is less about new nodes and more about operational reality: tool installs, uptime, and the painful gap between “first light” and stable yield. Intel’s latest update underscores a tilt toward tool spending and a clearer tie between High-NA and its 14A roadmap. Meanwhile, reporting around Samsung’s Taylor site points to EUV test operations starting in March, as AI-driven memory demand keeps the whole lithography ecosystem under pressure.Key takeaways:- Intel says near-term manufacturing output is constrained, with improvement expected as tool additions, yield work, and throughput gains take hold.- Intel is signaling a 2026 spend mix that prioritizes manufacturing tools over new cleanroom shell expansion.- Intel confirms High-NA EUV is targeted for its 14A process family, turning High-NA from a technology demo into a roadmap assumption.- Reports say Samsung will begin EUV tool test operations at its Taylor, Texas foundry site in March, ahead of planned H2 2026 production.- The Taylor reports also cite roughly 7,000 workers on-site daily and a push for temporary occupancy clearance, highlighting the “factory readiness” side of EUV.- Reuters reports Samsung plans to start HBM4 production next month for intended Nvidia supply, reinforcing AI memory as a structural driver of advanced patterning capacity.- ASML’s Q4 and full-year 2025 results arrive January 28, a near-term read on EUV mix and High-NA cadence.- Some details around Samsung’s Taylor timing and end-customer allocations are based on third-party reporting and remain unconfirmed by official Samsung statements.Glossary:Extreme Ultraviolet (EUV) lithography — 13.5 nm-wavelength lithography used for leading-edge patterning.High-NA — High numerical aperture EUV optics that improve resolution but tighten process control demands.Numerical aperture — A measure of an optical system’s ability to resolve fine features.First light — The milestone when an EUV tool produces usable exposure performance at a site.Overlay — Layer-to-layer alignment accuracy; a key yield driver at advanced nodes.Pellicle — A thin membrane that protects the EUV mask from particles while transmitting EUV light.Stochastic effects — Random photon and chemistry variations that can cause defects at very small feature sizes.Throughput — Practical wafer output of a tool or line, often constrained by uptime and dose requirements.Yield — The fraction of good dies per wafer; the ultimate test of process stability.This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

A modern chip looks simple from the outside, but it’s the end result of an industrial chain that starts with sand and ends with nanometer-accurate patterning in a cleanroom.In this episode we walk the full path, step by step, without over-focusing on any single stage.When we reach lithography, we use an EUV scanner as the concrete example.Key takeaways- Chipmaking is a repeating loop: add a film, pattern it, transfer it, measure it, and repeat.- Electronic-grade silicon often uses chlorosilane chemistry and distillation-based purification before silicon is redeposited as ultra-pure polysilicon.- Single-crystal ingots are grown (commonly by the Czochralski method) and sliced, polished, and flattened into wafers.- Cleaning and contamination control are as fundamental as any “core” process step.- Thin films are built by oxidation and deposition methods such as CVD, PVD, and ALD, each with different trade-offs.- EUV lithography uses 13.5 nm light, vacuum, and mirror optics; the light is generated by a tin plasma source.- Plasma etching translates resist patterns into device layers with trade-offs between selectivity, directionality, and uniformity.- Ion implantation and annealing create doped regions while balancing activation against thermal budget risks.- CMP keeps the wafer flat enough for lithography and multilayer integration, but introduces its own defect risks.- After BEOL wiring, wafers are tested, diced, packaged, and screened so only known-good parts ship.Glossary- Electronic-grade polysilicon: Ultra-pure polycrystalline silicon used as feedstock for crystal growth.- Czochralski growth: A method for pulling a single-crystal ingot from molten silicon using a seed crystal.- Photoresist: A light-sensitive polymer film used to form a temporary pattern during lithography.- EUV lithography: Patterning with 13.5 nm extreme ultraviolet light using reflective optics in vacuum.- Reticle (mask): The patterned template whose image is projected onto the wafer in a scanner.- Plasma etch (dry etch): Material removal in a plasma chamber using reactive species and ion bombardment.- Ion implantation: Doping by accelerating ions into a wafer to place impurities at controlled depth and dose.- Anneal: A thermal step used to repair damage and activate dopants or modify materials.- CMP: Chemical-mechanical planarization; a polishing step that restores wafer flatness.- BEOL: Back end of line; the multilayer metal interconnect stack that wires transistors together.This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

This week’s EUV story is told through purchases: TSMC’s stepped-up 2026 capex, Micron’s decision to buy an existing cleanroom in Taiwan, and a U.S. megafab that won’t ship wafers until 2030. We connect those signals to the real bottleneck behind two-nanometer ramps: stable EUV hours, masks, and metrology. And we look at why High-NA matters less as a resolution headline and more as a cycle-time lever.Key takeaways:- TSMC guided 2026 capex to US$52–56B, with 70–80% allocated to advanced process technology and 10–20% to advanced packaging, test, and mask making.- TSMC said its N2 (2nm) process entered high-volume manufacturing in 4Q 2025 at Hsinchu and Kaohsiung with good yield, with a faster ramp expected in 2026.- TSMC said N2P volume production is scheduled for 2H 2026 and A16 volume production is on track for 2H 2026.- TSMC said AI accelerators were a high-teens percentage of total revenue in 2025 and expects 2026 revenue growth close to 30% (USD terms).- Micron signed an LOI to acquire PSMC’s P5 site in Tongluo for US$1.8B, including 300,000 square feet of 300mm cleanroom space, with meaningful DRAM output targeted for 2H 2027.- Micron expects the Tongluo transaction to close by calendar Q2 2026, subject to agreements and regulatory approvals, and plans a phased DRAM equip-and-ramp.- Micron held a groundbreaking for its New York megafab project, describing a US$100B complex with production expected to start in 2030 and a goal of producing 40% of its DRAM in the U.S.- Culpium reported Apple is competing harder for leading-edge TSMC capacity as AI accelerator demand rises, with Nvidia potentially leading wafer purchases in some quarters.- Reuters noted ASML briefly topped a US$500B market capitalization amid the semiconductor rally following TSMC’s capex outlook.- No new official ASML EUV shipment or High-NA field update this week; the next major disclosure point is ASML’s January 28, 2026 results.Glossary:EUV — Extreme Ultraviolet lithography using 13.5 nm light for advanced patterning.High-NA — High numerical aperture EUV optics (0.55 NA) enabling finer imaging and fewer multi-patterning steps on critical layers.N2 — TSMC’s 2nm-class gate-all-around nanosheet process node.N2P — Performance-enhanced variant of N2 scheduled for 2H 2026.A16 — TSMC node featuring Super Power Rail (backside power delivery) targeting 2H 2026 volume production.Scanner hours — A practical capacity metric: usable time on lithography tools after uptime and yield constraints.Cleanroom — Ultra-controlled fab space whose construction, utilities, and staffing often limit expansion pace.Mask making — Fabrication of reticles used in lithography; a common bottleneck for EUV ramps.HBM — High Bandwidth Memory; stacked DRAM used with AI accelerators, driving demand for advanced DRAM capacity.Advanced packaging — 2.5D/3D integration techniques that link logic and memory and consume significant capex and engineering effort.This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

"3 nanometer." "2 nanometer." "18A." These labels sound like simple size numbers, but they are really product-family names that bundle transistor architecture, power delivery, design rules, and manufacturing maturity. This episode explains what a node actually means in the EUV era, why Intel/TSMC/Samsung nodes do not line up, and how economics pushes modern chips toward variants, chiplets, and advanced packaging.Key Takeaways- A node name is a brand, not a ruler; the nanometer label is not a single physical dimension.- Comparing nodes across companies by name alone is misleading; compare deliverables like transistor type, power delivery, and ramp maturity.- TSMC positions N2 as its first nanosheet (gate-all-around) node with volume production starting in late 2025, and A16 adds a backside-power concept (SPR).- Samsung's SF3 is a GAA-plus-EUV node, and Samsung has published a staged SF2 ramp plan (mobile first, then HPC and automotive).- Intel 4 is Intel's first production node using EUV, and Intel 18A pairs RibbonFET (GAA) with PowerVia (backside power) with a stated HVM target in 2H 2025.- DRAM "nodes" (1z, 1-alpha, 1-beta, 1-gamma, 1anm) are ten-nanometer-class generations, not comparable to logic nanometer labels; EUV is added selectively and increasingly.- NAND scaling is primarily about vertical layer count; more layers raise etch and yield complexity but improve bits per wafer.- EUV and High-NA EUV economics matter: tool cost, fab energy demand, and yield risk shape which products move first and why chiplets and packaging keep growing.Glossary- Node: A manufacturing generation name for a platform (rules, devices, interconnect, libraries, maturity), not a literal feature size.- PPA: Power, performance, area - shorthand foundries use to summarize expected node improvements.- FinFET: A transistor with a fin-shaped channel and a gate that wraps around multiple sides.- Gate-all-around (GAA): A transistor where the gate surrounds the channel more completely (often implemented as nanosheets/nanoribbons).- Nanosheet / nanoribbon: A GAA device shape using stacked thin channels to improve electrostatic control.- Backside power delivery: Routing power from the back of the wafer to reduce front-side routing congestion and improve power integrity.- EUV: Extreme ultraviolet lithography; used to pattern very small features, but it is capital- and energy-intensive.- HVM: High-volume manufacturing; the phase when a node is producing at scale with stable yields.- DRAM: Dynamic random-access memory; scaling is constrained by the repeating cell and capacitor/access-device integration.- NAND: Non-volatile flash memory; scaling is largely vertical (more layers) and limited by deep etch, deposition, and yield.This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

This week’s EUV conversation is about signals, not shipments: Intel ties its 18A node to a mainstream CES launch, ASML swats away a cybersecurity rumor, and imec frames 2026 as a race to compress learning cycles. With TSMC in a quiet period ahead of earnings, the industry is temporarily trading on inference — and that makes EUV capacity and High-NA readiness the real subtext.Key takeaways:- Intel positioned Panther Lake / Core Ultra Series 3 as a broadly adopted AI PC platform built on 18A, a test of high-volume manufacturing maturity.- CEO messaging around “going big time into 14A” signals continued node ambition and keeps EUV ecosystem planning active.- ASML said social-media claims of a data breach were untrue, underscoring the security perimeter around strategic lithography infrastructure.- No major new EUV scanner shipment announcements surfaced in the last several days.- TSMC’s quiet period ahead of its January 15 earnings call limits near-term public roadmap detail, so some demand signals remain indirect.- Imec’s 2026 strategy emphasizes XTCO, explicitly linking EUV progress to faster end-to-end learning across compute, memory, packaging, and interconnect.- Imec says a next-generation High-NA scanner is set to be installed in Leuven in 2026, expanding the ecosystem’s real-wafer learning capacity.- In 2026, “speed” in EUV increasingly means learning per quarter, not just wafers per hour.Glossary:EUV — Extreme ultraviolet lithography using ~13.5 nm wavelength light for leading-edge patterning.High-NA — High numerical aperture EUV optics enabling tighter imaging for smaller pitches.18A — Intel process node branding associated with a leading-edge manufacturing generation.XTCO — Cross-technology co-optimization; jointly optimizing device, interconnect, packaging, power, and thermals.Edge placement error — Combined pattern placement uncertainty that drives yield and performance at small geometries.Stochastic defects — Random, shot-noise-driven patterning failures that become more visible at extreme pitches.Overlay — Alignment accuracy between successive lithography layers.OPC — Optical proximity correction; computational pattern adjustments to print intended shapes on wafer.Pellicle — Thin membrane protecting EUV masks from particles while withstanding high-power exposure.This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

Transistors are the “switches” inside every modern processor, but they aren’t just tiny on/off buttons. In this episode, we build an intuition for how MOSFET transistors work, and why EUV lithography matters even though it doesn’t change the transistor’s basic physics. We then take a quick tour of the leading-edge shift from FinFETs to gate-all-around nanosheet devices, plus what’s coming next.Key takeaways- A MOSFET controls current by using a gate electric field to create or remove a thin conductive channel between source and drain.- “Off” is never perfectly off: subthreshold leakage is fundamental and becomes harder to suppress as devices shrink.- Performance and energy are increasingly limited by capacitances, contact resistance, and interconnect, not just the channel itself.- EUV lithography uses 13.5 nm light, reflective optics, and vacuum, enabling tight patterning for advanced nodes.- EUV introduces stochastic variability (randomness) that shows up as roughness and occasional pattern failures at tiny dimensions.- FinFETs wrap the gate on three sides of a fin for better control than planar transistors.- Gate-all-around nanosheet transistors wrap the gate fully around the channel, improving electrostatics and offering flexible drive strength.- The leading edge is converging on GAA plus improved power delivery (including backside concepts) plus more advanced EUV tools (High-NA) where it makes sense.Glossary- Transistor: A device that controls current flow; in logic chips it functions as a switch.- MOSFET: A transistor where a gate electric field modulates a channel through an insulating dielectric.- Gate / Source / Drain: The control terminal (gate) and the two terminals between which current flows (source and drain).- Channel (inversion layer): The thin conductive region created under the gate that allows current to flow.- FinFET: A 3D MOSFET where the gate wraps around a silicon fin on three sides to improve control.- GAA / nanosheet: Gate-all-around transistor where the gate surrounds thin silicon sheets that form the channel.- EUV lithography: Patterning with 13.5 nm light using reflective optics in vacuum to print very small features.- High-NA EUV: A newer EUV generation with higher numerical aperture (0.55) for better resolution and contrast.- Backside power delivery: Routing power on the wafer backside to reduce congestion and power drop in front-side wiring.This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

EUV The Focal Point delivers updates on the global semiconductor industry. The podcast explains key developments in EUV and (High-)NA lithography, leading-edge logic nodes, DRAM and HBM. It follows the strategies of ASML, Intel, TSMC, Samsung, SK Hynix, Micron and Rapidus. Clear, concise and accessible. For everyone who wants to understand how advanced chips are built and why they shape the global economy.This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

EUV The Focal Point delivers updates on the global semiconductor industry. The podcast explains key developments in EUV and (High-)NA lithography, leading-edge logic nodes, DRAM and HBM. It follows the strategies of ASML, Intel, TSMC, Samsung, SK Hynix, Micron and Rapidus. Clear, concise and accessible. For everyone who wants to understand how advanced chips are built and why they shape the global economy.This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

EUV The Focal Point delivers updates on the global semiconductor industry. The podcast explains key developments in EUV and (High-)NA lithography, leading-edge logic nodes, DRAM and HBM. It follows the strategies of ASML, Intel, TSMC, Samsung, SK Hynix, Micron and Rapidus. Clear, concise and accessible. For everyone who wants to understand how advanced chips are built and why they shape the global economy.This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

The Integrated Circuit (IC), also known as a microchip or simply chip, is a compact assembly of electronic circuits—such as transistors, resistors, and capacitors—and their interconnections, fabricated onto a thin, flat piece of semiconductor material, most commonly silicon. Compared to assemblies built from discrete components, ICs are orders of magnitude smaller, faster, more energy-efficient, and less expensive, and have revolutionized modern technology. The development began in 1958 with Jack Kilby, who successfully demonstrated the first working example. Robert Noyce developed the first practical monolithic silicon IC chip in 1959. Modern chips utilize Very-Large-Scale Integration (VLSI) and may contain billions of transistors.This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

EUV The Focal Point delivers updates on the global semiconductor industry. The podcast explains key developments in EUV and (High-)NA lithography, leading-edge logic nodes, DRAM and HBM. It follows the strategies of ASML, Intel, TSMC, Samsung, SK Hynix, Micron and Rapidus. Clear, concise and accessible. For everyone who wants to understand how advanced chips are built and why they shape the global economy.This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

The CO2 laser, invented in 1964, is one of the most useful and highest-power continuous-wave gas lasers currently available, emitting in the infrared region (wavelengths centering on 9.6 and 10.6 micrometers (μm)). Traditionally, it is used in industrial applications for cutting, welding, and engraving, as well as in surgery for soft-tissue procedures.Currently, the CO2 laser plays a decisive role in EUV lithography for manufacturing the latest generation of microchips. The TRUMPF Laser Amplifier is a pulsed CO2 laser system that strikes 50,000 tin droplets per second inside a vacuum chamber. This process creates an intensive plasma, which emits Extreme Ultraviolet (EUV) radiation with an optimal wavelength of 13.5 nanometers.Components such as the High Power Seed Module (HPSM) are essential for optimally shaping the pulses and ensuring the commercial viability of EUV technology. ASML recently honored TRUMPF for a new EUV high-energy laser that is scheduled for series production starting in 2026. This laser is intended to increase the availability and power of the EUV products while contributing to lower energy consumption.This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

EUV The Focal Point delivers updates on the global semiconductor industry. The podcast explains key developments in EUV and (High-)NA lithography, leading-edge logic nodes, DRAM and HBM. It follows the strategies of ASML, Intel, TSMC, Samsung, SK Hynix, Micron and Rapidus. Clear, concise and accessible. For everyone who wants to understand how advanced chips are built and why they shape the global economy.This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

In this podcast episode, we discuss numerical aperture (NA) in EUV lithography - perhaps the most important lever for resolution and feature size on modern chips. We explain what NA means in physical terms, how it affects resolution and depth of field, and why the leap from “low NA” to “high NA” is a game changer for future technology nodes. We also highlight the impact of higher NA on scanner design, process windows, and cost per wafer - and why this directly influences the strategies of manufacturers such as ASML, Intel, and TSMC. This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

EUV The Focal Point delivers updates on the global semiconductor industry. The podcast explains key developments in EUV and (High-)NA lithography, leading-edge logic nodes, DRAM and HBM. It follows the strategies of ASML, Intel, TSMC, Samsung, SK Hynix, Micron and Rapidus. Clear, concise and accessible. For everyone who wants to understand how advanced chips are built and why they shape the global economy.This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

EUV The Focal Point delivers updates on the global semiconductor industry. The podcast explains key developments in EUV and High-NA lithography, leading-edge logic nodes, DRAM and HBM. It follows the strategies of ASML, Intel, TSMC, Samsung, SK Hynix, Micron and Rapidus. Clear, concise and accessible. For everyone who wants to understand how advanced chips are built and why they shape the global economy.This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

EUV lithography (EUVL) is the key technology for continuing chip miniaturization. It uses extremely short-wavelength light (13.5 nm) to expose the finest structures. This sophisticated process is the result of close cooperation between ASML (systems), ZEISS (optics), and TRUMPF (lasers). TRUMPF high-power lasers generate plasma from tin droplets 50,000 times per second, which emits the EUV light. Since EUV radiation is absorbed by air, the entire process runs in a vacuum with the aid of ultra-precise multilayer mirrors. ASML is the sole manufacturer and enables production for 3 nm nodes. Future high-NA systems (0.55 NA) are expected to achieve 2 nm nodes. This article was created with the help of AI. Please verify the information if you intend to use it as a basis for your decision-making. This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

EUV The Focal Point delivers updates on the global semiconductor industry. The podcast explains key developments in EUV and High-NA lithography, leading-edge logic nodes, DRAM and HBM. It follows the strategies of ASML, Intel, TSMC, Samsung, SK Hynix, Micron and Rapidus. Clear, concise and accessible. For everyone who wants to understand how advanced chips are built and why they shape the global economy.This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.