Main Trust Issue in FPGA HLS Design Workflow

This episode examines ContractHIL-HLS, a paper from Jingbo Zhang and colleagues at Beijing University of Technology (posted to arXiv July 28, 2026) that tackles high-level synthesis for FPGA design, where LLM-generated hardware can compile cleanly and pass simulation yet still fail on real silicon due to timing violations, routing congestion, or power overruns that only surface during actual synthesis and place-and-route. The discussion contrasts this work with prior efforts like Chip-Chat, RTLLM, and HLS-Eval, arguing those prove models can generate hardware code but not that a workflow can reliably preserve design intent and incorporate tool feedback across multiple steps. Rather than relying on conversational role-prompting, where constraints can silently drift or vanish between turns, the paper's architecture splits agents by transformation type — a Contract Agent converts natural language into a structured object with named fields for interface, constraints, and validation policy, an HTML Agent renders it stably, and a Hardware-in-the-Loop Agent implements and revises designs using real Vitis HLS synthesis, Vivado place-and-route, and board bring-up rather than trusting the model's own claims. The hosts debate whether structured fields actually prevent drift better than conversational memory does, landing on the distinction that a missing field is inspectable while conversational drift is not, though enforcement remains an open question. Listeners interested in how hardware-design automation might borrow validation rigor from aerospace and control-systems engineering will find the explanation of Hardware-in-the-Loop testing, and its adaptation to catch AI-generated designs before they reach costly physical fabrication, especially compelling. Sources: 1. ContractHIL-HLS: Contract-Aligned Multi-Agent Workflow with Hardware-in-the-Loop Feedback for HLS Design — Jingbo Zhang, Haoxiang Sun, Wenbo Wang, Wenbo Zhang, 2026 http://arxiv.org/abs/2607.25283 2. LegUp: High-Level Synthesis for FPGA-Based Processor/Accelerator Systems — Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Anderson, Stephen Brown, Tomasz Czajkowski, 2011 (FPGA conference; extended in ACM TODAES 2013) https://scholar.google.com/scholar?q=LegUp%3A+High-Level+Synthesis+for+FPGA-Based+Processor%2FAccelerator+Systems 3. Fast Inference of Deep Neural Networks in FPGAs for Particle Physics (hls4ml) — Javier Duarte, Song Han, Philip Harris, et al., 2018 https://scholar.google.com/scholar?q=Fast+Inference+of+Deep+Neural+Networks+in+FPGAs+for+Particle+Physics+%28hls4ml%29 4. Chip-Chat: Challenges and Opportunities in Conversational Hardware Design — Jason Blocklove, Siddharth Garg, Ramesh Karri, Hammond Pearce, 2023 https://scholar.google.com/scholar?q=Chip-Chat%3A+Challenges+and+Opportunities+in+Conversational+Hardware+Design 5. AutoChip: Automating HDL Generation Using LLM Feedback — Shailja Thakur et al., 2023 https://scholar.google.com/scholar?q=AutoChip%3A+Automating+HDL+Generation+Using+LLM+Feedback 6. MnasNet: Platform-Aware Neural Architecture Search for Mobile — Mingxing Tan, Bo Chen, Ruoming Pang, Vijay Vasudevan, Mark Sandler, Andrew Howard, Quoc V. Le, 2019 https://scholar.google.com/scholar?q=MnasNet%3A+Platform-Aware+Neural+Architecture+Search+for+Mobile 7. FBNet: Hardware-Aware Efficient ConvNet Design via Differentiable Neural Architecture Search — Bichen Wu, Xiaoliang Zhang, Kaiwen Weng, Yandong Guo, Peizhao Zhang, Yanghan Wang, Kurt Keutzer, Peter Vajda, 2019 https://scholar.google.com/scholar?q=FBNet%3A+Hardware-Aware+Efficient+ConvNet+Design+via+Differentiable+Neural+Architecture+Search 8. Learning Dexterous In-Hand Manipulation — OpenAI (Marcin Andrychowicz, Bowen Baker, Maciek Chociej, Rafal Jozefowicz, et al.), 2020 (IJRR; earlier preprint 2018) https://scholar.google.com/scholar?q=Learning+Dexterous+In-Hand+Manipulation 9. CRYSTALS-Kyber: A CCA-Secure Module-Lattice-Based KEM — Joppe Bos, Léo Ducas, Eike Kiltz, Tancrède Lepoint, Vadim Lyubashevsky, John M. Schanck, Peter Schwabe, Gregor Seiler, Damien Stehlé, 2018 https://scholar.google.com/scholar?q=CRYSTALS-Kyber%3A+A+CCA-Secure+Module-Lattice-Based+KEM 10. A Compact Hardware Implementation of CCA-Secure Key Exchange Mechanism CRYSTALS-KYBER on FPGA — Yufei Xing, Shuguo Li, 2021 https://scholar.google.com/scholar?q=A+Compact+Hardware+Implementation+of+CCA-Secure+Key+Exchange+Mechanism+CRYSTALS-KYBER+on+FPGA 11. Module-Lattice-Based Key-Encapsulation Mechanism Standard (FIPS 203) — National Institute of Standards and Technology (NIST), 2024 https://scholar.google.com/scholar?q=Module-Lattice-Based+Key-Encapsulation+Mechanism+Standard+%28FIPS+203%29 12. KyberMat and CRYPHTOR (accelerator designs cited directly in the ContractHIL-HLS paper) — Not independently verified here — cited by the ContractHIL-HLS authors as references [8] and [9], Recent (post-2023, exact years unconfirmed) https://scholar.google.com/scholar?q=KyberMat+and+CRYPHTOR+%28accelerator+designs+cited+directly+in+the+ContractHIL-HLS+paper%29 13. HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks — S. Abi-Karam, C. Hao, 2025 https://scholar.google.com/scholar?q=HLS-Eval%3A+A+Benchmark+and+Framework+for+Evaluating+LLMs+on+High-Level+Synthesis+Design+Tasks 14. SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation — M. Z. S. Khan, N. Mashnoor, M. Akyash et al., 2025 https://scholar.google.com/scholar?q=SAGE-HLS%3A+Syntax-Aware+AST-Guided+LLM+for+High-Level+Synthesis+Code+Generation 15. A Prompt Pattern Catalog to Enhance Prompt Engineering with ChatGPT — J. White, Q. Fu, S. Hays et al., 2023 https://scholar.google.com/scholar?q=A+Prompt+Pattern+Catalog+to+Enhance+Prompt+Engineering+with+ChatGPT 16. Evaluating Large Language Models Trained on Code — M. Chen, J. Tworek, H. Jun et al. (OpenAI Codex/HumanEval), 2021 https://scholar.google.com/scholar?q=Evaluating+Large+Language+Models+Trained+on+Code 17. KyberMat: Efficient Accelerator for Matrix-Vector Polynomial Multiplication in CRYSTALS-Kyber via NTT and Polyphase Decomposition — W. Tan, Y. Lao, K. K. Parhi, 2023 https://scholar.google.com/scholar?q=KyberMat%3A+Efficient+Accelerator+for+Matrix-Vector+Polynomial+Multiplication+in+CRYSTALS-Kyber+via+NTT+and+Polyphase+Decomposition Interactive Visualization: Main Trust Issue in FPGA HLS Design Workflow