Optimizing Data Center Design from 'Chip to Chiller'

The data center industry is leaving enormous value on the table by failing to apply chip-level simulation techniques to the full infrastructure stack, argues Sherman Ikemoto of Cadence. Closing the “chip-to-chiller” design gap is now an existential requirement, given the pace of AI compute density growth. In an in-depth Cool Vector interview, Cadence’s Group Director of Business Development describes how “the timescales to build chips, and to build the facilities that house the chips, are totally different. So there's this natural massive gap in the design chain.” Key takeaways from Ikemoto’s interview: • If data center developers are able to compress a 24-month AI factory standup to 18 or 16 months, that translates directly into billions of dollars of accelerated return. • For three decades, rack power density grew ~10% annually. In the AI era, it has jumped to 60–100% per year—an order-of-magnitude acceleration that fundamentally breaks traditional data center cooling technologies and design methodologies. • Backing off GPU power utilization by 10–20% frees up enough headroom to add more GPUs to the same power envelope. Access the full transcript and a searchable content library at the Cool Vector Substack: https://coolvector.substack.com/p/from-chip-to-chiller?r=4tjd55 #datacenter #digitalinfrastructure #ai