Storage Developer Conference

Compute Express Link™ (CXL™) is an industry-supported cache-coherent interconnect for processors, memory expansion, and accelerators. Datacenter architectures are evolving to support the workloads of emerging applications in Artificial Intelligence and Machine Learning that require a high-speed, low latency, cache-coherent interconnect. The CXL specification delivers breakthrough performance, while leveraging PCI Express® technology to support rapid adoption. It addresses resource sharing and cache coherency to improve performance, reduce software stack complexity, and lower overall systems costs, allowing users to focus on target workloads. Attendees will learn how CXL technology maintains a unified, coherent memory space between the CPU (host processor) and CXL devices allowing the device to expose its memory as coherent in the platform and allowing the device to directly cache coherent memory. This allows both the CPU and device to share resources for higher performance and reduced software stack complexity. In CXL, the CPU host is primarily responsible for coherency management abstracting peer device caches and CPU caches. The resulting simplified coherence model reduces the device cost, complexity and overhead traditionally associated with coherency across an I/O link. Learning Objectives: Learn how CXL supports dynamic multiplexing between a rich set of protocols that includes I/O (CLX.io, based on PCIe®), caching (CXL.cache), and memory (CXL.mem) semantics.,Understand how CXL maintains a unified, coherent memory space between the CPU and any memory on the attached CXL device,Gain insight into the features introduced in the CXL specification

Improvements to the SMB3.1.1 client on Linux have continued at a rapid pace over the past year. These allow Linux to better access Samba server, as well as the Cloud (Azure), NAS appliances, Windows systems, Macs and an ever increasing number of embedded Linux devices including those using the new smb3 kernel server Linux (ksmbd). The SMB3.1.1 client for Linux (cifs.ko) continues to be one of the most actively developed file systems on Linux and these improvements have made it possible to run additional workloads remotely. The exciting recent addition of the new kernel server also allows more rapid development and testing of optimizations for Linux. Over the past year, performance has dramatically improved with features like multichannel (allowing better parallelization of i/o and also utilization of multiple network devices simultaneously), with much faster encryption and signing, with better use of compounding and improved support for RDMA. Security has improved and alternative security models are now possible with the addition of modefromsid and idsfromsid and also better integration with Kerberos security tooling. New features have been added include the ability to swap over SMB3 and boot over SMB3. Quality continues to improve with more work on 'xfstests' and test automation - tooling (cifs-utils) continue to be extended to make use of SMB3.1.1 mounts easier. This presentation will describe and demonstrate the progress that has been made over the past year in the Linux kernel client in accessing servers using the SMB3.1.1 family of protocols. In addition recommendations on common configuration choices, and troubleshooting techniques will be discussed. Learning Objectives: What new features are now possible when accessing servers from Linux?,What new tools have been added to make it easier to use SMB3.1.1 mounts from Linux?,What new features are nearing completion that you should you expect to see in the near future?,How can I configure the security settings I need to use SMB3.1.1 for my workload?,How can I configure the client for optimal performance for my workload?

The NVMe Key Value (NVMe-KV) Command Set has been standardized as one of the new I/O Command Sets that NVMe Supports. Additionally, SNIA has standardized a Key Value API that works with the NVMe Key Value allows access to data on a storage device using a key rather than a block address. The NVMe-KV Command Set provides the key to store a corresponding value on non-volatile media, then retrieves that value from the media by specifying the corresponding key. Key Value allows users to access key-value data without the costly and time-consuming overhead of additional translation tables between keys and logical blocks. This presentation will discuss the benefits of Key Value storage, present the major features of the NVMe-KV Command Set and how it interacts with the NVMe standards, and present open source work that is available to take advantage of Key Value storage. Learning Objectives: Present the standardization of SNIA KV API,Present the standardization of NVMe Key Value Command Set,Present the benefits of Key Valeu in computational storage,Present open source work on Key Value Storage.

The rapid improvement of overall $/Gbyte has driven the high performance All-Flash Array to be increasingly adopted in both enterprises and cloud datacenters. Besides the raw NAND density scaling with continued semiconductor process improvement, data reduction techniques have and will play a crucial role in further reducing the overall effective cost of All-Flash Array. One of the key data reduction techniques is compression. Compression can be performed both inline and offline. In fact, the best All-Flash Arrays often do both: fast inline compression at a lower compression ratio, and slower, opportunistic offline deep compression at significantly higher compression ratio. However, with the rapid growth of both capacity and sustained throughput due to the consolidation of workloads on a shared All-Flash Array platform, a growing percentage of the data never gets the opportunity for deep compression. There is a deceptively simple solution: Inline Deep Compression with the additional benefits of reduced flash wear and networking load. The challenge, however, is the prohibitive amount of CPU cycles required. Deep compression often requires 10x or more CPU cycles than typical fast inline compression. Even worse, the challenge will continue to grow: CPU performance scaling has slowed down significantly (breakdown of Dennard scaling), but the performance of All-Flash Array has been growing at a far greater pace. In this talk, I will explain how we can meet this challenge with a domain-specific hardware design. The hardware platform is a FPGA-based PCIe card that is programmable. It can sustain 5+Gbyte/s of deep compression throughput with low latency for even small data block sizes (TByte/s BW and less than 10ns of latency) and the almost unlimited parallelism available on a modern mid-range FPGA device. The hardware compression algorithm is trained with a vast amount of data available to our systems. Our benchmarks show it can match or outperform some of the best software compressors available in the market without taxing the CPU. Learning Objectives: Hardware Architecture for Inline Deep Compression,Design of Hardware Deep Compression Engine,Inline and offline compression of All-Flash Array.

Zoned Namespaces represent the first step towards the standardization of Open-Channel SSD concepts in NVMe. Specifically, ZNS brings the ability to implement data placement policies in the host, thus providing a mechanism to lower the write-amplification factor (WAF), (ii) lower NAND over-provisioning, and (iii) tighten tail latencies. Initial ZNS architectures envisioned large zones targeting archival use cases. This motivated the creation of the "Append Command” - a specialization of nameless writes that allows to increase the device I/O queue depth over the initial limitation imposed by the zone write pointer. While this is an elegant solution, backed by academic research, the changes required on file systems and applications is making adoption more difficult. As an alternative, we have proposed exposing a per-zone random write window that allows out-of-order writes around the existing write pointer. This solution brings two benefits over the “Append Command”: First, it allows I/Os to arrive out-of-order without any host software changes. Second, it allows in-place updates within the window, which enables existing log-structured file systems and applications to retain their metadata model without incurring a WAF penalty. In this talk, we will cover in detail the concept of the random write window, the use cases it addresses, and the changes we have done in the Linux stack to support it. Learning Objectives: Learn about general ZNS architecture and ecosystem,Learn about the use cases supported in ZNS and the design decisions in the current specification with regards to in-place updates and multiple inflight I/Os,Learn about new features being brought to NVMe to support in-place updates and transparent hight queue depths.

The Software-Enabled Flash API gives unprecedented control to application architects and developers to redefine the way they use flash for their hyperscale applications, by fundamentally redefining the relationship between the host and solid-state storage. Dive deep into new Software-Enabled Flash concepts such as virtual devices, Quality of Service (QoS) domains, Weighted Fair Queueing (WFQ), Nameless Writes and Copies, and controller offload mechanisms. This talk by KIOXIA (formerly Toshiba Memory) will include real-world examples using the new API to define QoS and latency guarantees, workload isolation, minimize write amplification by application-driven data placement, and achieve higher performance with customized flash translation layers (FTL). Learning Objectives: Provide an in-depth dive into using the Software Enabled Flash API,Map application workloads to Software Enabled Flash structures,Understand how to implement QoS requirements using the API.

The NVM Express workgroup is introducing new features frequently, and the Linux kernel supporting these devices evolves with it. These ever moving targets create challenges when developing tools when new interfaces are created, or older ones change. This talk will provide information on some of these recent features and enhancements, and introduce the open source 'libnvme' project which implements an open source library available in public git repositories that provides access to all NVM Express features with convenient abstractions to the kernel interfaces interacting with your devices. The session will demonstrate integrating the library with other programs, and also provide an opportunity for the audience to share what additional features they would like to see out of this common library in the future. Learning Objectives: Explain protocol and host operating system interaction complexities,Introduce libnvme and how it manages those relationships,Demonstrate integration with applications.

The efficiency, performance and choice in NVMe-oF is enabling some very unique and interesting use cases – from AI/ML to Hyperconverged Infrastructures. Artificial Intelligence workloads process massive amounts of data from structured and from unstructured sources. Today most deep learning architectures rely on local NVMe to serve up tagged and untagged datasets into map-reduce systems and neural networks for correlation. NVMe-oF for Deep Learning infrastructures enables a shared data model to ML/DL pipelines without sacrificing overall performance and training times. NVMe-oF is also enabling HCI deployment to scale without adding more compute, enabling end customers to reduce dark flash and reduce cost. The talk explores these and several innovative technologies driving the next storage connectivity revolution. Learning Objectives: Storage architectures for Deep Learning Workloads,Extending the reach of HCI platforms using NVMe-oF,Ethernet Bunch of Flash architectures.

NVMe is the fastest growing storage technology of the last decade and has succeeded in unifying client, hyperscale and enterprise applications into a common storage framework. NVMe has evolved from a being a disruptive technology to becoming a core element in storage architectures. In this session, we will talk about the NVMe transition to a merged base specification inclusive of both NVMe and NVMe-oF architectures. We will provide an overview of the latest NVMe technologies, summarize the NVMe standards roadmap and describe the latest NVMe standardization initiatives. NVMe technology will present a number of areas of innovation that preserve our simple, fast, scalable paradigm while extending the broad appeal of NVMe architecture. These continued innovations will ready the NVMe technology ecosystem for yet another period of growth and expansion. Learning Objectives: Learn about the NVMe transition to a merged base specification inclusive of both NVMe and NVMe-oF architectures. Receive a summary of the NVMe standards roadmap,Understand the latest NVMe standardization initiatives.

With PMEM boasting a much higher density and DRAM-like performance, applying it to in-memory caching such as memcached seems like an obvious thing to try. Nonetheless, there are questions when it comes to new technology. Would it work for our use cases, in our environment? How much effort does it take to find out if it works? How do we capture the most value with reasonable investment of resource? How can we continue to find a path forward as we make discoveries? At Twitter, we took an iterative approach to explore cache on PMEM. With significant early help from Intel, we started with simple tests in memory mode in a lab environment, and moved on to app_direct mode with modifications to Pelikan (pelikan.io), a modular open-source cache backend developed by Twitter. With positive results from the lab runs, we moved the evaluation to platforms that more closely represent Twitter’s production environment, and uncovered interesting differences. With better understanding of how Twitter’s cache workload behaves on the new hardware, and our insight into Twitter’s cache workload in general, we are proposing a new cache storage design called Segcache that, among other things, offers flexibility with storage media and in particular is designed with PMEM in mind. As a result, it achieves superior performance and effectiveness when running either on DRAM or PMEM. The whole exploration was made easier by the modular architecture of Pelikan, and we added a benchmark framework to support the evaluation of storage modules in isolation, which also greatly facilitated our exploration and development. Learning Objectives: Demonstrate the feasibility of using PMEM for caching and meeting production requirements. Provide a case study on how software companies can approach and adopt new technology like PMEM iteratively. Provide observations and suggestions on how to promote a more integral hardware/software design cycle.

Software-based memory-to-memory data movement is common, but takes valuable cycles away from application performance. At the same time, offload DMA engines are vendor-specific and may lack capabilities around virtualization and user-space access. This talk will focus on how SDXI(Smart Data Acceleration Interface), a newly formed SNIA TWG is working to bring an extensible, virtualizable, forward-compatible, memory to memory data movement and acceleration interface specification. As new memory technologies get adopted and memory fabrics expand the use of tiered memory, data mover acceleration and its uses will increase. This TWG will encourage adoption and extensions to this data mover interface. Learning Objectives: A new proposed standard for a memory to memory data movement interface,A new TWG to develop this standard,Usecases where this will apply to evolving storage architecture with memory pooling and persistent memory

Since the advent of the Smart Phone over a decade ago, we've seen several new "Smart" technologies, but few have had a significant impact on the data center until now. SmartNICs and SmartSSDs will change the landscape of the data center, but what comes next? This talk will summarize the state of the SmartNIC market by classifying and discussing the technologies behind the leading products in the space. Then it will dive into the emerging technology of SmartSSDs and how they will change the face of storage and solutions. Finally, we'll dive headfirst into the impact of PCIe 5 and Compute Express Link (CXL) on the future of Smart Acceleration on solution delivery. Learning Objectives: Understand the current state of the SmartNIC market & leading products.,Introduce the concept of SmartSSDs and two products available today.,Discuss the future of Device to Device (D2D) communications using PCIe, CXL/CCIX.,Lay out a vision for where composable solutions leveraging multiple devices on a PCIe buss communicating directly.

The ZFS L2ARC is now more than 10 years old. Over that time, a lot of secret incantations and tribal knowledge have been created by users, testers, developers, and the odd sales or marketing person. That collection of community wisdom informs the use and/or tuning of ZFS L2ARC for certain IO profiles, dataset sizes, server class, share protocols, and device types. In this talk, we will review a case study in which we tested a few of these L2ARC myths on an NVMe-capable OpenZFS storage appliance. Can high-speed NVMe flash devices keep L2ARC relevant in the face of ever-increasing memory capacity for ARC (primary cache) and all-flash storage pools? Learning Objectives: 1) Overview of ZFS L2ARC design goals and high level implementation details that pertain to our findings; 2) Performance characteristics of L2ARC during warming and when warmed, plus any tradeoffs or pitfalls with L2ARC in these states; 3) How to leverage NVMe as L2ARC devices to improve performance in a few storage use cases.

5G Wireless technology will bring vastly superior data rates to the edge of the network. However, with this increase in bandwidth will come applications that significantly increase overall network throughput. Video applications will likely explode as end users have large amounts of data bandwidth to operate. Video will not only require advanced compression but will require large amounts of data storage. Combining advanced compression technologies with storage will allow a high density of storage and compression in a small amount of rack space with little power, ideal for placement at the edge of the network. NVMe based module provides the opportunity to use computational storage elements to enable edge compute and video compression. This presentation will provide technical details and various options to combine video and storage on an NVMe interface. Further, it will explore how this NVMe device can be virtualized for both storage and video in an edge compute environment. Learning Objectives: 1) Understand how NVMe can be used for both video and storage; 2) Understand how computational storage can be virtualized using NVMe; 3) Understand why combinational element modules such as Video Storage will become important after deployment of 5G networks.

By now, you have a good understanding of SNIA Swordfish™ and how it extends the DMTF Redfish® specification to manage storage equipment and services. Attend this presentation to learn what’s new and how the specification has evolved since last year. The speaker will share the latest updates ranging from details of features and profiles to new vendor-requested functionality that’s supporting the specification from direct-attached to NVMe. You won’t want to miss this opportunity to be brought up-to-speed. Learning Objectives: 1) Educate the audience on what’s new with Swordfish; 2) Describe features and profiles and why they are useful; 3) Provide an overview of vendor-requested Swordfish functionality.

DMTF's Redfish® is a standard API designed to deliver simple and secure management for converged, hybrid IT and the Software Defined Data Center (SDDC). Both human readable and machine capable, Redfish leverages common Internet and web services standards to expose information directly to the modern tool chain. This presentation will provide an overview of Redfish, what’s new in the Redfish ecosystem, as well as adoption in the broader standards community. You’ll also learn more about the general Redfish data model, including the base storage models and infrastructure that are used by SNIA Swordfish extensions. Learning Objectives: 1) Introduce the DMTF Redfish API; 2) Provide an update on the latest Redfish developments; 3) Understand how SNIA Swordfish builds on Redfish.

The SNIA NVMP TWG continues to make significant progress on defining the architecture for interfacing applications to PM. In this talk, we will focus on the important Remote Persistent Memory scenario, and how the NVMP TWG’s programming model applies. Application use of these interfaces, along with fabric support such as RDMA and platform extensions, are part of this, and the talk will describe how the larger ecosystem fits together to support PM as low-latency remote storage.

Whether you are a storage vendor, consumer, or developer, the performance of storage solutions affects you. Assessing the performance of large and complex storage solutions requires some level of performance testing lab, and there are many factors to consider. From network topology to load generator CPU, all components must be selected and configured with care to avoid unintended bottlenecks. In this session, we will review a few best practices and lessons learned, including: whether virtual clients are feasible and my experiences attempting performance testing on several different hypervisors, best practices for network configuration, and how to use maximum effective data rates to avoid unintended bottlenecks. Finally, we will conclude with a review of data comparing different physical load generating hardware and its effect on measured performance. Learning Objectives: 1) Effect of load generating client hardware on measured performance; 2) Avoiding unintended bottlenecks by using interconnect maximum effective data rates; 3) Best practices for configuring a performance lab network and load generators.

SMB 3.1.1 is the state of the art for secure remote file access, but deploying it for clouds and mobile users can be very challenging; TCP/445 is often blocked, networks are often slow, and edge file servers are often feared. The Microsoft SMB3 team has now built the first implementation of SMB3 over QUIC, a UDP/TLS transport pioneered by Google. This allows secure tunneling of SMB3 over internet-friendly ports. Furthermore, we have added compression for SMB3, which allows significant data savings over congested and low bandwidth networks. In this talk we’ll discuss these new options, as well as other recent security and feature capabilities nearing completion. Learning Objectives: 1) SMB3 over new transport; 2) SMB3 over wide area networks; 3) SMB3 protocol update.

Attendees of this presentation will learn how to use several open source tools ( https://github.com/jharriga/ ) to evaluate object storage platforms. These tools provide automation and customer-based object storage workloads for activities such as filling a cluster, aging a cluster and running steady-state mixed operation workloads. One of the tools, RGWtest, automates pool creation, logs cluster statistics such as system resource utilization (CPU and memory) and submits workloads through COSbench - Intel’s open source object storage benchmark tool. A demonstration of the tools will be part of the presentation. Learning Objectives: 1) How to install, configure and execute the object storage workload tools; 2) How to interpret workload run results; 3) How to design and size object storage workloads.

PowerShell is a task-based command-line shell and scripting language that helps rapidly automate tasks that manage operating systems (Linux, macOS, and Windows) and processes. PowerShell is open-source, object-based and includes a rich expression parser and a fully developed scripting language with a gentle learning curve. The PowerShell Toolkit for SNIA Swordfish™ provides simple to use commands for managing any Swordfish Implementation (including the SNIA API Emulator). Attend this session to learn how to use the SNIA Swordfish PowerShell Module to jumpstart development of your own Swordfish implementation. Learning Objectives: 1) Provide an overview of the PowerShell open source tool kit; 2) Describe how the PowerShell tool kit can speed a Swordfish implementation; 3) Educate the audience on how to use and access the PowerShell tool kit.

After a year of implementation progress of the The SMB3 .1.1 POSIX Extensions, a set of protocol extensions to allow for optimal Linux and Unix interoperability with NAS and Cloud file servers - what is the current status - what have we learned - what has changed in the protocol specification in the past year - what advice do we have for implementers - and users … These extensions greatly improve the experience for users of Linux. This presentation will review the state of the protocol extensions and their current implementation in the Linux kernel and Samba among others, and provide an opportunity for feedback and suggestions for additions to the POSIX extensions. This has been an exciting year with many improvements to the implementations of the SMB3.1.1 POSIX Extensions in Samba and Linux! Learning Objectives: 1) What is the current status of Linux interoperability with various SMB3.1.1 servers?; 2) How have the protocol extensions for Linux/POSIX progressed over the past year? What has changed? What works?; 3) What are suggestions for implementors of SMB3.1.1 servers?; 4) What is useful information for users to know to try these extensions?; 5) How do new Linux file system features map to these extensions?

NVMe KV (Key-Value) is an industry-wide proposal for a new command structure that allows access to data on an NVMe SSD controller using a “key” rather than a block address. Developed within the NVM Express technical working group, this Key Value command set provides a “key” to store a corresponding “value” on non-volatile media, then retrieves that “value” from the media by specifying the corresponding “key.” In addition to extensive work being undertaken by the NVM Express working group, the SNIA has completed an overarching KeyValue API released for a membership vote in January 2019. This presentation examines standardization efforts going on within SNIA and the NVM Express working group that will allow users to access key-value data without the costly and time-consuming overhead of additional translation tables between keys and logical blocks. Learning Objectives: 1) What is the status of standards development; 2) Overview of what is in the SNIA KV API; 3) Overview of what is in the NVMe KV proposal.

A variety of persistent memory technologies with DRAM-class performance, known as “memory class storage” or “MCS”, have appeared on the horizon. MCS will change the architecture of future computing systems. These technologies include carbon nanotube memory, phase change memory, magnetic spin memory, and resistive memory, and each has unique characteristics that can complicate systems designed to exploit them. The JEDEC DDR5 NVRAM specification in process intends to bridge the differences between the technologies and provide systems designers with a unified specification for DRAM-class persistent memory. Nantero NRAM is a NVRAM based on carbon nanotube cell structures that provides a DDR4 or DDR5 interface to the system, and provides additional enhancements to yield 20% higher performance at the same clock rate. Learning Objectives: 1) Attendees are exposed to system level advantages of memory class storage devices that operate at DRAM speeds but provide data persistence; 2) JEDEC is working on a new specification to standardize the interface to a variety of NVRAMs which provide memory class storage; 3) Nantero NRAM is a memory class storage device with better than DRAM performance.

One of the most common benchmarks in the storage industry is 4KiB random read I/O per second. Over the years, the industry first saw the publication of 1M I/Ops on a single box, then 1M I/Ops on a single thread (by SPDK). More recently, there have been publications outlining 10M I/Ops on a single box using high performance NVMe devices and more than 100 CPU cores. This talk will present a benchmark of SPDK performing more than 10 million random 4KiB read operations per second from a single thread to 20 NVMe devices, a large advance compared to the state of the art of the industry. SPDK has developed a number of novel techniques to reach this level of performance, which will be outlined in detail here. These techniques include polling, advanced MMIO doorbell batching strategies, PCIe and DDIO considerations, careful management of the CPU cache, and the use of non-temporal CPU instructions. This will be a low level talk with real examples of eliminating data dependent loads, profiling last level cache misses, pre-fetching, and more. Additionally, there remains a number of techniques that have not yet been employed that warrant future research. These techniques often push devices outside of their original intended operating mode, while remaining within the bounds of the specification, and so often require collaboration between NVMe controller and device designers, the NVMe specification body, and software developers such as the SPDK team. Learning Objectives: 1) Optimal use of NVMe devices; 2) Optimal use of PCIe and MMIO in a storage stack; 3) Leveraging advanced x86-64 CPU instructions and making best use of the CPU cache.

The applications using NVMe, SAS, SATA, USB based storage devices find a new use and one of them is mining for open source cryptocurrency such as Burst Coin. Using low power or solar power HDD’s, SSD and most importantly NVMe technology can improve turnaround latency and build blocks on a faster scale. Utilization of security protocols allows anonymization as well as protection of the users and vendors. Burst coin has an extensive developer’s community and can run on the cloud, has dApps, its own ATM and more. More importantly, Burst is based on Proof of Capacity protocol and utilizes storage drives, arrays and enables users to build the mesh net of miners and secure blockchain protocol. Using NVMe devices we can accelerate transactions. We will show how using performance analytics tools we can create predictions on building blockchain blocks and provide insights into date usage efficiency. Additional value benefits are saving energy costs, address new markets and create adoption in the larger markets. The usage of storage devices and blockchain will enable HW secure banking transactions (via smart contracts) and much more. Learning Objectives: 1) Learn how Proof of Capacity works with storage devices; 2) Find new applications for Storage applications; 3) Understand Data Science perception with Blockchain.

A growing trend in the market is capacity of data. This data growth is creating challenges within modern storage infrastructures and a new way to think of data is needed. The SNIA Computational Storage TWG was formed in October of 2018 to address this opportunity for the Storage industry to use innovative technologies that bring computational capabilities closer to or within the storage device. The goal of the TWG is to develop an architecture and set of definitions that allow for common communication about the problem set as well as a standardized interface between the Computational Storage device and host or peer devices. Ultimately the TWG will drive standardization of the necessary Computational Storage interfaces across the industry, contribute to and drive the development of software necessary to enable the usages, and promote the education of the industry regarding Computational Storage. This session will provide an overview of Computational Storage, the focus areas of the TWG, and the opportunities for engagement with the rest of the industry in this space. Learning Objectives: 1) Overview of the Computational Storage TWG goals; 2) Walk through the current architectural paradigms defined in the TWG; 3) Give the industry a common language to speak regarding computational storage.

Last year at SDC we reviewed the integration of crypto which made use of DPDK’s existing variety of drivers to usher in the capability. This year we are expanding our use of DPDK with the addition of a compression! This talk will outline the overall architecture of the compression module and explain in detail how we are managing the layout of the device and leveraging the Persistent Memory Development Kit to store metadata in super-fast persistent memory. Learning Objectives: 1) Understand new SPDK compression feature; 2) Understand the value of SPDK in general; 3) Learn about the SPDK Community.

This talks explains the exciting new features in the Linux NVMe driver and software target in the last two years, as well as the relevant block layer changes to support these features. Learning Objectives: 1) Learn about new Linux features; 2) Learn about new NVMe features; 3) Have fun!

LTO (Linear Tape Open) is an industry standard format for tape drives and media. To begin this talk we will give a brief overview of LTO tape: how data is recorded and accessed on tape, and some characteristics that make it very different from earlier forms of computer tape storage. We will then discuss the current state of LTO tape, including “feeds and speeds”, backwards/forwards drive and media compatibility, and the LTO Consortium’s roadmap for the future. Finally, we’ll discuss the Linear Tape File System (LTFS): what it is, how it works, and what benefits it provides. We’ll end with a detailed description of the latest important feature in LTFS version 2.5, Incremental Indexes, including a discussion of the impetus for Incremental Indexes, the benefits they provide, and an explanation of how they work. This talk is suitable for newcomers to tape storage as well as those who are already taking advantage of LTO tape and LTFS. Learning Objectives: 1) Understand the operation and current state of LTO tape storage, and its roadmap for the future; 2) Understand the use and benefits of the Linear Tape File System (LTFS); 3) Learn how adding Incremental Indexes to LTFS improves performance and storage efficiency while preserving backwards compatibility.

Introducing pmemkv, an open-source local key/value store for persistent memory based on PMDK. Written in C/C++, pmemkv provides optimized language bindings for Java, JavaScript, and Ruby. Pmemkv includes multiple storage engines that are tailored for different use-cases. Fast, flexible and bulletproof, pmemkv is an easy way to modify applications to use persistent memory. Learning Objectives: 1) Learn about a local/embedded key-value data store optimized for persistent memory; 2) Learn how cloud applications can easily manage key/value data on persistent platforms; 3) Code samples that demonstrate the ease of use of different language bindings.

RocksDB, a high performance key-value database developed by Facebook, has proven effective in using the high data speeds made possible by Solid State Drives (SSDs). By leveraging the NVMe standard, Eideticom’s NoLoad® presents FPGA computational storage processors as NVMe namespaces to the operating system and enables efficient data transfer between the NoLoad® Computational Storage Processors (CSPs), host memory and other NVMe/PCIe devices in the system. Presenting Computational Storage Processors as NVMe namespaces has the significant benefit of minimal software effort to integrate computational resources. In this presentation we use Eideticom’s NoLoad® to speed up RocksDB. Compared to software compaction running on a Dell R7425 PowerEdge server, our NoLoad®, running on Xilinx’s Avleo U280, resulted in 6x improvement in database transactions and 2.5x reduction is CPU usage while reducing worst case latency by 2.7x. Learning Objectives: 1) Computational storage with NVMe; 2) Presenting computational storage processors as NVMe namespaces; 3) Accelerating database access with NVMe computational storage processors.

Since the first release of NVMe 1.0 in 2011, the NVMe family of specifications continue to expand to support current and future storage markets, increasing the amount of new features and functionality. With that natural, organic growth, however, comes additional complexity. In order to refocus on simplicity and ease-of-development, the NVM Express group has undertaken a massive effort to refactor the specification. The upcoming refactored specification - NVMe 2.0 - integrates the scalable and flexible NVMe over Fabrics architecture within the NVMe base specification, meeting the needs of platform designers, device vendors and developers. But how can developers optimally design their products using the new NVMe 2.0 specification? This session will provide attendees with the following insights: • An overview of the existing specification structure, its logic and limitations • Highlights on how developers use the current specification before refactoring • Information showing how the refactored specification enables companies to architect their products with better awareness of future areas of innovation • Details on how new features and functionalities will be included in the refactored specification • Descriptions of how developers can leverage the refactored NVMe 2.0 specification to simply and efficiently bring new products to market • Examination of the current projects and how to contribute Learning Objectives: 1) Overview of the current NVMe specification structure; 2) Introduction to NVMe 2.0: the refactored specification enables companies and developers to simply and efficiently bring new products to market; 3) The new features and functionalities that will be included in NVMe 2.0 and how to get involved in current projects.

Over the years, SSD QoS has become more important to a variety of storage market segments. Traditional latency reporting methods do not always accurately depict QoS behaviors. This is problematic when attempting to understand what events lead to a specific QoS level and how to mitigate latency events that lead to levels of QoS. Defining correct statistical techniques for large populations of latencies deepens our understanding of what drives levels of QoS. Advanced statistical techniques, such a machine learning and utilizing AI, allows for deeper understanding of what drives QoS and how to correctly manage large quantities of latencies. New visualization techniques enhance capabilities to understand latency behavior and define critical scenarios that drive latency. Learning Objectives: 1) Identify shortcomings of current QoS reporting; 2) Generate more reliable QoS values; 3) Techniques to broaden understanding of groups of latencies; 4) Identification of critical transitions in latency; 5) Identify inaccuracies that inhibit understanding QoS.

With the onset of the Computational Storage TWG and growth of interest in the market for these new and emerging solutions, it is imperative to understand how to develop, deploy and scale these new technologies. This session will walk through the new definitions, how each can be deployed and show use cases of NGD Systems Computational Storage Devices (CSD). Learning Objectives: 1. Learn the different kinds of Computational Storage 2. Understand the use cases for each type of solutions 3. Determine the ease of deployment and the value of these solutions

SMB3 has seen significant adoption as the storage protocol of choice for running private cloud deployments. With the recent advances in persistent memory technologies, we will take a look at how we can leverage the SMB3 protocol in conjunction with SMBDirect/RDMA to provide very low latency access to persistent memory devices across the network. With the increasing popularity of cloud storage - technologies like Azure Files which provide seamless access to cloud stored data via the standard SMB3 protocol is seeing significant interest. One of the key requirements in this space is to be able to run SMB3 over a secure / firewall friendly internet protocol. We will take a quick look at some work we are doing to enable SMB3 over QUIC - which is a recent UDP based transport with strong security and interop properties. We will also explore some work we have done to enable on-the-wire compression for SMB3. Learning Objectives: 1) Learn how we can use SMB3 to setup direct RDMA access to remote persistent memory; 2) Using QUIC as a transport for SMB3; 3) How can we use data compression algorithms to optimize SMB data transfer?

This talk describes work going on in three different organizations to enable scale out management of NVMe SSDs. The soon to be released NVME-MI 1.1 standard will allow management from host based agents as well as BMCs. This might be extended to allow support for Binary Encoded JSON (BEJ) in support of host agents and BMCs that want to support the Redfish Standard. We will also cover work going on in SNIA (Object Drive TWG) and DMTF in support. Learning Objectives: 1) Principles and limitations of scale out datacenter management; 2) An understanding of the NVMe-MI standard; 3) A Redfish profile for NVMe drives; 4) Inside the box management networks and outside the box management networks; 5) Platform Layer Data Model (PLDM).

As NVDIMMs enter the realm of standard equipment on servers and storage arrays and NVMe is standard equipment for servers and consumer devices alike, what is the actual performance advantage of using NVDIMM over NVMe, or NVMe over SAS or SATA SSDs? First, we’ll review some purely synthetic benchmarks of single devices using different storage technologies and see how they differ. Then, we’ll enter a more real world environment and see what performance gains can be had. One use of NVDIMMs is as a transaction log to allow quick acknowledgement of write operations. In our real-world scenario, we discuss the performance differences of using NVDIMMs, NVMe Flash, or SAS/SATA Flash as the SLOG or “write-cache” for an OpenZFS pool. Learning Objectives: 1) Performance differences between different storage media and storage transports for transactional workloads; 2) Basic overview of OpenZFS and how a SLOG works; 3) Impact of low latency NVDIMM and NVMe storage for application and user latency.

The Storage Performance Development Kit (SPDK) open source project is gaining momentum in the storage industry for its drivers and libraries for building userspace, polled mode storage applications and appliances. The SPDK NVMe driver was SPDK’s first released building block and is its most well-known. The driver’s design and architecture is heavily influenced by SPDK’s userspace polled-mode framework which has resulted in some significant differences compared to traditional kernel NVMe drivers. This presentation will present an overview of the SPDK NVMe driver’s architecture and design, a historical perspective on key design decisions and a discussion on the driver’s advantages and limitations. Learning Objectives: 1) Gain a deeper understanding of the architecture and design of the SPDK NVMe driver; 2) Identify the key design differences between a userspace polled-mode driver and a traditional kernel-mode driver; 3) Describe the key advantages and limitations of SPDK and its polled mode NVMe driver.

Persistent Memory is getting a lot of attention. SNIA has released a programming standard, NVDIMM makers, with the help of JEDEC, have created standardized hardware to develop & test PM, and chip makers continue to promote upcoming devices, although few are currently available. In this talk two industry analysts, Jim Handy & Tom Coughlin, will provide the state of Persistent Memory and show a realistic roadmap of what the industry can expect to see and when they can expect to see it. The presentation, based on three critical reports covering New Memory Technologies, NVDIMMs, and Intel’s 3D XPoint Memory (also known as Optane) will illustrate the Persistent Memory market, the technologies that vie to play a role, and the critical economic obstacles that continue to impede these technologies’ progress. We will also explore how advanced logic process technologies are likely to cause persistent memories to become a standard ingredient in embedded applications, such as IoT nodes long before they make sense in servers. Learning Objectives: 1) What is the state of emerging memory technologies; 2) What technologies will be used in future NVDIMMS; 3) Emerging memory use in embedded and enterprise applications; 4) What are the costs for making emerging memories.

Applying micro service patterns to storage giving each workload its own Container Attached Storage (CAS) system. This puts the DevOps persona within full control of the storage requirements and brings data agility to k8s persistent workloads. We will go over the concept and the implementation of CAS, as well as its orchestration. Learning Objectives: 1) Go over the modern day apps and their storage needs; under the notion of applications have changed someone forgot to tell storage; 2) What are the problems to use technologies like user space IO, in particular using technologies like SPDK among others; 3) Looking devops and the k8s model, how can we bring the power of user space storage in developers hands? Virtio for containers? direct access from the go run time for example SPDK?; 4) We have tried both, and like to share the outcome of this with you.

Increasing proliferation of Artificial Intelligence, E-commerce, Big Data and Cloud applications is leading to highly diversified workloads and use cases in hyperscale data centers, which poses new challenges to solid state storage in terms of performance, flexibility and TCO optimizations. Moreover, there are increasing demands for software/hardware co-optimization and more control over I/O path from applications. Standard SSDs that are tuned for a few generic workloads cannot meet these challenges, resulting in suboptimal performance and TCO. We present our Dual-Mode SSD Architecture, a new storage architecture designed for our next-generation hyperscale data centers. We define our Open Channel SSD specification and build a Dual-Mode SSD platform that supports both Open Channel mode and standard NVMe mode. We develop our Open Channel software stack in full user space as well as in kernel space. Working seamlessly with our storage engine software, we build customized FTL solutions for different business applications. Our software/hardware co-optimization solutions is leading to significant benefits in performance, Quality-of-Service and TCO. Learning Objectives: 1) Challenges to solid storage systems in next-generation hyperscale data centers; 2) Dual-Mode SSD architecture; 3) Full user space Open Channel software stack, and software/hardware co-optimization solutions.

The talk covers (i) the characteristics of open-channel SSD management, (ii) introduces the new open-channel/Denali interface, (iii) provides background on LightNVM, the Linux subsystem that we designed and implemented for open-channel SSD management, and at last, we show the effectiveness of open-channel SSDs against state-of-art block-based SSDs. Learning Objectives: 1) Understand Open-Channel SSDs; 2) Project status; 3) Background on storage and applications.

PCI Express® (PCIe®) 3.0 architecture has enabled Flash Storage to transition to high speed, low latency power efficient performance over the past few years. However, the hunger for additional performance in power constrained devices continues and PCI-SIG® continues its nearly three decade history of delivering performance doubling and additional features with the development of the PCIe 4.0 and PCIe 5.0 specifications. This presentation will review the major features of PCIe 4.0 and PCIe 5.0 technology, which will continue to enable power efficient performance required as NAND capacities scale and faster SCM (Storage Class Memories) become mainstream. Session attendees will gain insight into the current status of the PCIe 4.0 technology rollout and testing and will learn about the PCIe 5.0 specification development and timeline for completion in 2019. Learning Objectives: 1) Learn how PCIe is becoming the I/O of choice for storage; 2) Gain insight into the status of PCIe 4.0 roll-out for storage applications; 3) Understand the PCIe roadmap to 32GT/s.

Many server workloads, for example OLTP database workloads, require high I/O throughput and low latency. With the industry trend of moving high-end scale-up workloads to virtualization environment, it is essential for cloud providers and on-premises servers to achieve near native performance by reducing I/O virtualization overhead which mainly comes from two sources: DMA operations and interrupt delivery mechanism for I/O completions. The direct PCIe NVMe device assign techniques allow a VM to interact with HW devices directly and avoid using traditional Hyper-V para-virtualized I/O path. To improve interrupt handling in the virtualization environment, Intel introduces Posted Interrupts (PI) as an enhanced method to mitigate interrupt delivery overhead in a virtualized environment, bypassing hypervisor involvement completely. In this talk, we will present Microsoft implementation and optimization of Intel PI and Hyper-V direct PCIe NVMe access on Windows platform. The results showed that we were able to achieve more than 10-Million IOPS from a single VM for the first time in the industry using an Intel Skylake based HPE commodity server with these techniques.

Have you heard of non-volatile/persistent memory but don’t know how to get started with this disruptive technology? Memory is the new Storage. Next generation storage tiered architectures are evolving with persistent memory and hardware delivering NVDIMMs. Are you a Linux or Windows application developer familiar with C, C++, Java, or Python, keen to develop the next revolutionary application or modify an existing application, but not sure where to start? Do you know what performance and analysis tools can be used to identify optimizations in your app to take advantage of persistent memory? Are you a software, server, or cloud architect that wants to get a jump start on this disruptive technology? This presentation will get you started on the persistent memory solution path. The future is in your hands. The future is now! Learning Objectives: 1) We’ll deliver an introductory understanding of persistent memory, introduce the SNIA Programming Model, Direct Access (DAX) filesystems, and show where persistent memory fits in the storage hierarchy; 2) We’ll provide several options for creating development environments (you don’t need physical modules to get started!); 3) We’ll introduce application programming using the Persistent Memory Developers Kit (PMDK); 4) We’ll introduce and describe how to create and manage Persistent Memory Regions, Namespaces, and Labels; 5) Describe existing analysis tools to identify applications that are good candidates for persistent memory.

In-situ processing, in-storage processing, smart SSD, computational storage… Many names to define the same concept: a closer integration of computing capabilities and data storage in order to reduce data movement leading to better performance and lower power consumption. This is a new trend in storage and computing architectures. How can we define this new type of products: storage with embedded processing, or processing with embedded storage? This talk presents an analysis of the in-storage processing trend, including a comparison of different architectures, the presentation of a computing and storage technologies roadmap, and a list of applications use cases. Learning Objectives: 1) In-storage processing architectures; 2) Technology roadmap for integration; 3) Application use cases.

The SNIA NVMP Technical Workgroup (TWG) continues to make significant progress on defining the architecture for interfacing applications to PM. In this talk, we will focus on the important Remote Persistent Memory scenario, and how the NVMP TWG’s programming model applies. Application use of these interfaces, along with fabric support such as RDMA and platform extensions, are part of this, and the talk will describe how the larger ecosystem fits together to support PM as low-latency remote storage. Learning Objectives: 1) Persistent Memory programming; 2) RDMA extensions; 3) SNIA PM initiatives.

Ceph protects data by making 2-3 copies of the same data but that means 2-3x more storage servers and related costs. It also means higher write latencies as data hops between OSD nodes. Customers are now starting to deploy Ceph using SSDs for high-performance workloads and for data lakes supporting real-time analytics. We describe a novel approach that eliminates the added server cost by creating Containerized, stateless OSDs and leveraging NVMe-over-fabrics to replicate data in server-less storage nodes. We propose redefining the boundaries of separation within SDS architectures to address disaggregation overheads. Specifically, we decouple control and data plane operations and transfer block ownership to execute on remote storage targets. It also dramatically reduces write latency to enable Ceph to be used for databases and to speed up large file writes. As part of the solution, we also describe how OSD node failover is preserved via a novel mechanism using standby stateless OSD nodes. Learning Objectives: 1) Storage disaggregation; 2) NVMe over fabrics; 3) Ceph architecture.

NVMe and NVMe over Fabrics (NVMe-oF) protocols provide a highly efficient access to flash storage inside a server and over the network respectively. Current generation of distributed storage software stacks use proprietary protocols which are sub-optimal to deliver end to end low latency. Moreover it increases operational complexity to manage NVMe-oF managed flash storage and distributed flash storage in private cloud infrastructure. In this session, we present NVMe over Fabrics based high performance distributed block storage that combines the best of both worlds to deliver performance, elasticity and rich data services. Learning Objectives: 1) NVMe, NVMe-oF for flash data path IO architecture; 2) Programming, architecture and optimization for flash; 3) Distributed storage, data services.