All Episodes
Condor Currents — 60 episodes
A Spatio-Temporal Expert Prefetching Framework for Efficient MoE-based LLM Inference
Tiara: A Programmable Line-Rate ISA for Remote Memory Access
Isolation-aware Scheduling Framework for DNN-based End-to-End Autonomous Driving System on Tile-based Accelerators
Energy-Efficient On-Device RAG on a Mobile NPU: System Design and Benchmark on Snapdragon X Elite
SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network Accelerators through Co-Optimized Mapping and Scheduling
NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire
Toward Intelligent Prefetching: A Survey on Complex Memory Access Prediction Techniques
MOSAIC: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs
ANNS-AMP: Accelerating Approximate Nearest Neighbor Search via Adaptive Mixed-Precision Computing
BIDENT: Heterogeneous Operator-level Mapping for Efficient Edge Inference
AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp
Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library
Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures
RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware
Regular-Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures
FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Superscalar Processor with Tomasulo-Style Dynamic Scheduling
Co-Designing Graph-based Approximate Nearest Neighbor Search at Billion Scale for Processing-in-Memory
Sustainable Real-Time 8K60 HEVC Encoding for V2X: Repurposing Legacy NVENC Hardware at the Vehicular Edge
Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation
Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation
Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation
OSCAR: Offline Spectral Covariance-Aware Rotation for 2-bit KV Cache Quantization
How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum
Enhancing Instruction Prefetching via Cache and TLB Management
SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software
RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware
RISC-V Vector Extension: Between standardization and tailor-made accelerators - eeNews Europe
SPEC CPU2026: Characterization, Representativeness, and Cross-Suite Comparison
RV-IM100: Quantifying ISA Extension, Datapath Width, and Pipeline Depth Trade-offs in RISC-V Microarchitectures
Optimizing Branch Predictor for Graph Applications
RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
Ragged Paged Attention: A High-Performance and Flexible LLM Inference Kernel for TPU
Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday
EPAC: The Last Dance
DEEP-GAP: Deep-learning Evaluation of Execution Parallelism in GPU Architectural Performance
Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - notebookcheck.net
QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society
A Precision Emulation Approach to the GPU Acceleration of Ab Initio Electronic Structure Calculations
Throughput Optimization as a Strategic Lever in Large-Scale AI Systems: Evidence from Dataloader and Memory Profiling Innovations
Highly-Parallel Atom-Detection Accelerator for Tweezer-Based Neutral Atom Quantum Computers
Per-Bank Memory Bandwidth Regulation for Predictable and Performant Real-Time System
Current RISC-V CPUs Being Too Slow Causes Headaches For Fedora: ~5x Slower Builds - Phoronix
The RISC-V Vector Extensions for AI - jonpeddie.com
Vividnode Mobile AI Packs RISC-V Processor and 60 TOPS AI Engine - LinuxGizmos.com
TRINE: A Token-Aware, Runtime-Adaptive FPGA Inference Engine for Multimodal AI
TorR: Towards Brain-Inspired Task-Oriented Reasoning via Cache-Oriented Algorithm-Architecture Co-design
PAI: Fast, Accurate, and Full Benchmark Performance Projection with AI
Alibaba delivers RISC-V server chip optimized to run China’s top AI models
SpacemiT K3 "16-core" RISC-V SoC system information and (early) benchmarks - CNX Software
As Alibaba launches server-grade RISC-V CPU, Beijing throws its weight behind ISA - theregister.com
Mitigating the Bandwidth Wall via Data-Streaming System-Accelerator Co-Design
An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
NVIDIA Ports CUDA to RISC-V, Betting Big on Open-Source ISA - TechPowerUp
Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
Machine Learning-Driven Intelligent Memory System Design: From On-Chip Caches to Storage
RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual
RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual
Multi-Agent Memory from a Computer Architecture Perspective: Visions and Challenges Ahead
Mitigating the Memory Bottleneck with Machine Learning-Driven and Data-Aware Microarchitectural Techniques