Condor Currents

## Episode Summary In this episode, we cover: - **A Spatio-Temporal Expert Prefetching Framework for Efficient MoE-based LLM Inference** (arXiv) - **MADAR: An Address-Free Processor** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **Support RAJA and Scientific Applications on RVV Architectures** (riscv_news) - **Synergy Quantum Unveils Quantum-Safe Silicon IP Cores for RISC-V-Based SoCs - PR Newswire** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Tiara: A Programmable Line-Rate ISA for Remote Memory Access** (arXiv) - **HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verification** (arXiv) - **Using a Performance Model to Implement a Superscalar CVA6** (riscv_news) - **Ben C.'s Clever Compiler Imports Verilog Designs, Including a Working RISC-V CPU, Into Factorio - Hackster.io** (google_riscv) - **Now you can put a SpacemiT K3 RISC-V processor in a Framework Laptop 13 - Liliputing** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Isolation-aware Scheduling Framework for DNN-based End-to-End Autonomous Driving System on Tile-based Accelerators** (arXiv) - **Non-Parametric Dual-Manifold Mapping via 8-Bit Bounded Transformation Matrices: Challenging FP-centric Hardware Paradigms in Low-Energy AI** (arXiv) - **160-core RISC V Board Is The M.2 CoProcessor You Didn’t Know You Needed - Hackaday** (google_riscv) - **Microchip Upgrades Its Mi-V RV32 RISC-V Soft-Core Processor, Promises a Major Speed Boost - Hackster.io** (google_riscv) - **SpacemiT to launch server-class RISC-V processor following capital injection - South China Morning Post** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Energy-Efficient On-Device RAG on a Mobile NPU: System Design and Benchmark on Snapdragon X Elite** (arXiv) - **A Hybrid Edge-Cloud Architecture for Low-Latency Entitlement Verification in Resource-Constrained Devices** (arXiv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - TechPowerUp** (google_riscv) - **Security Researchers Find Current RISC-V CPU Implementations Coming Up Short - Phoronix** (google_riscv) - **AI is stress-testing processor architectures and RISC-V fits the moment - EDN - Voice of the Engineer** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network Accelerators through Co-Optimized Mapping and Scheduling** (arXiv) - **Partitioned Tags, Shared Data: Reconciling Strict Cache Isolation with Write-Shared Coherence** (arXiv) - **Intel Panther Lake Technical Deep Dive - Compute Tile: CPU Architecture - TechPowerUp** (google_arch) - **Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core - CNX Software** (google_riscv) - **The next RISC-V processor frontier: AI - EDN - Voice of the Engineer** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv) - **NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor - Quantum Zeitgeist** (google_riscv) - **NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor - Quantum Zeitgeist** (google_arch) - **NextSilicon to Productize Arbel RISC-V Core into 64-Core Enterprise Processor for AI and HPC - HPCwire** (google_arch) - **AI agent designs a complete RISC-V CPU from a 219-word spec sheet in just 12 hours — comparably simple design required 'many tens of billions of tokens' - Tom's Hardware** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Toward Intelligent Prefetching: A Survey on Complex Memory Access Prediction Techniques** (arXiv) - **SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC** (arXiv) - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - The National Law Review** (google_riscv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Eagle-Tribune** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **MOSAIC: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs** (arXiv) - **NetKV: Network-Aware Decode Instance Selection for Disaggregated LLM Inference** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **As Alibaba launches server-grade RISC-V CPU, Beijing throws its weight behind ISA - The Register** (google_riscv) - **Vortex 3.0 Released As Full-Stack, Open-Source RISC-V GPU Now With 3D Pipeline - Phoronix** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **ANNS-AMP: Accelerating Approximate Nearest Neighbor Search via Adaptive Mixed-Precision Computing** (arXiv) - **MOSAIC: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs** (arXiv) - **Evaluating and Calibrating Performance On RISC-V Vector Processors (KTH, LLNL, BSC) - Semiconductor Engineering** (google_riscv) - **Breker Verification Systems and Frontgrade Gaisler Collaborate on High-Reliability RISC-V Fault Tolerant Processor Core - Business Wire** (google_riscv) - **Prompt to tape out: Autonomous AI agent builds 1.5 GHz RISC-V CPU - Adafruit** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **BIDENT: Heterogeneous Operator-level Mapping for Efficient Edge Inference** (arXiv) - **Multi-Segment Attention: Enabling Efficient KV-Cache Management for Faster Large Language Model Serving** (arXiv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **A Deep Dive Into CPU Architecture - i-programmer.info** (google_arch) - **India Launches DHRUV64, Its First 1 GHz, 64-bit Dual-Core RISC-V CPU - TechPowerUp** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch) - **How RISC-V CPUs and GPUs Are Reshaping High-Performance SoCs in 2026 - News and Statistics - IndexBox** (google_riscv) - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv) - **India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - The Register** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library** (google_riscv) - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - Wccftech** (google_arch) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch) - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - Electropages** (google_arch) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures** (arXiv) - **CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees** (arXiv) - **The key CPU architecture you've never heard of: RISC-V - Red Shark News** (google_arch) - **RISC-V Vector Extension: Between standardization and tailor-made accelerators - eeNews Europe** (google_riscv) - **A RISC-V vector extension primer - Adafruit** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware** (google_riscv) - **Nvidia's CUDA platform now supports RISC-V — support brings open source instruction set to AI platforms, joining x86 and Arm - Tom's Hardware** (google_riscv) - **White paper: The All-Big-Core CPU Architecture of MediaTek Dimensity 9300 - MediaTek** (google_arch) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch) - **China claims to have developed the world's first AI-designed processor — LLM turned performance requests into CPU architecture - Tom's Hardware** (google_arch) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Regular-Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures** (arXiv) - **Observation, Not Prediction: Conversation-Level Disaggregated Scheduling for Agentic Serving** (arXiv) - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual** (riscv_news) - **One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon** (riscv_news) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Superscalar Processor with Tomasulo-Style Dynamic Scheduling** (arXiv) - **Code size reduction by advanced near addressing modes** (arXiv) - **Evaluating RISC-V Vector Processors: GCC vs. LLVM Autovectorization Benchmarks (May 2026) - News and Statistics - IndexBox** (google_riscv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **Support RAJA and Scientific Applications on RVV Architectures** (riscv_news) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Co-Designing Graph-based Approximate Nearest Neighbor Search at Billion Scale for Processing-in-Memory** (arXiv) - **Code size reduction by advanced near addressing modes** (arXiv) - **AI agent designs complete RISC-V CPU core autonomously - MSN** (google_riscv) - **CPU Instruction Set Architecture (ISA) Market - Market Growth Reports** (google_arch) - **Using a Performance Model to Implement a Superscalar CVA6** (riscv_news) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Sustainable Real-Time 8K60 HEVC Encoding for V2X: Repurposing Legacy NVENC Hardware at the Vehicular Edge** (arXiv) - **PoisonCap: Efficient Hierarchical Temporal Safety for CHERI** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_riscv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation** (arXiv) - **NasZip: Software and Hardware Co-Design to Accelerate Approximate Nearest Neighbor Search with DIMM-Based Near-Data Processing** (arXiv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **A Deep Dive Into CPU Architecture - i-programmer.info** (google_arch) - **AI agent designs a RISC-V CPU core from scratch - MSN** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation** (arXiv) - **NasZip: Software and Hardware Co-Design to Accelerate Approximate Nearest Neighbor Search with DIMM-Based Near-Data Processing** (arXiv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **A Deep Dive Into CPU Architecture - i-programmer.info** (google_arch) - **AI agent designs a RISC-V CPU core from scratch - MSN** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation** (arXiv) - **NasZip: Software and Hardware Co-Design to Accelerate Approximate Nearest Neighbor Search with DIMM-Based Near-Data Processing** (arXiv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **A Deep Dive Into CPU Architecture - i-programmer.info** (google_arch) - **160-core RISC V Board Is The M.2 CoProcessor You Didn’t Know You Needed - Hackaday** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **OSCAR: Offline Spectral Covariance-Aware Rotation for 2-bit KV Cache Quantization** (arXiv) - **TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing** (arXiv) - **Four-Tier Memory Hierarchy for LLM Reasoning (USC, UW)** (semiengineering) - **As Alibaba launches server-grade RISC-V CPU, Beijing throws its weight behind ISA - The Register** (google_riscv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv) - **India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - The Register** (google_riscv) - **AI designs complete RISC-V CPU core in just 12 hours - MSN** (google_riscv) - **India Launches DHRUV64, Its First 1 GHz, 64-bit Dual-Core RISC-V CPU - TechPowerUp** (google_riscv) - **Microchip Upgrades Its Mi-V RV32 RISC-V Soft-Core Processor, Promises a Major Speed Boost - Hackster.io** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Enhancing Instruction Prefetching via Cache and TLB Management** (arXiv) - **ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses** (arXiv) - **Evaluating and Calibrating Performance On RISC-V Vector Processors (KTH, LLNL, BSC)** (semiengineering) - **Evaluating and Calibrating Performance On RISC-V Vector Processors (KTH, LLNL, BSC) - Semiconductor Engineering** (google_riscv) - **CacheMind turns chip tuning into a conversation, exposing hidden cache failures and lifting processor performance - Tech Xplore** (google_arch) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **Nvidia's CUDA platform now supports RISC-V — support brings open source instruction set to AI platforms, joining x86 and Arm - Tom's Hardware** (google_riscv) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware** (google_riscv) - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - Wccftech** (google_arch) - **China claims to have developed the world's first AI-designed processor — LLM turned performance requests into CPU architecture - Tom's Hardware** (google_arch) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **RISC-V Vector Extension: Between standardization and tailor-made accelerators - eeNews Europe** (google_riscv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **Support RAJA and Scientific Applications on RVV Architectures** (riscv_news) - **RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual** (riscv_news) - **One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon** (riscv_news) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **SPEC CPU2026: Characterization, Representativeness, and Cross-Suite Comparison** (arXiv) - **Beyond Static Policies: Exploring Dynamic Policy Selection for Single-Thread Performance Optimization** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_riscv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **RV-IM100: Quantifying ISA Extension, Datapath Width, and Pipeline Depth Trade-offs in RISC-V Microarchitectures** (arXiv) - **SPEC CPU2026: Characterization, Representativeness, and Cross-Suite Comparison** (arXiv) - **A Deep Dive Into CPU Architecture - i-programmer.info** (google_arch) - **AI Agent Designs a RISC-V CPU Core From Scratch - IEEE Spectrum** (google_riscv) - **AI agent designs complete RISC-V CPU core autonomously - MSN** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Optimizing Branch Predictor for Graph Applications** (arXiv) - **A Comparative Analysis of ARM and x86-64 Laptop-Class Processors: Architecture, Assembly-Level Performance, and Energy Efficiency** (arXiv) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch) - **India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - theregister.com** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification** (arXiv) - **VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs** (arXiv) - **Nvidia's CUDA platform now supports RISC-V — support brings open source instruction set to AI platforms, joining x86 and Arm - Tom's Hardware** (google_riscv) - **China claims to have developed the world's first AI-designed processor — LLM turned performance requests into CPU architecture - Tom's Hardware** (google_arch) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Ragged Paged Attention: A High-Performance and Flexible LLM Inference Kernel for TPU** (arXiv) - **Overmind NSA: A Unified Neuro-Symbolic Computing Architecture with Approximate Nonlinear Activations and Preemptive Memory Bypass** (arXiv) - **RISC-V Vector Extension: Between standardization and tailor-made accelerators - eeNews Europe** (google_riscv) - **RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware** (google_riscv) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **Support RAJA and Scientific Applications on RVV Architectures** (riscv_news) - **RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual** (riscv_news) - **One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon** (riscv_news) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **EPAC: The Last Dance** (arXiv) - **Strix: Re-thinking NPU Reliability from a System Perspective** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_riscv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **DEEP-GAP: Deep-learning Evaluation of Execution Parallelism in GPU Architectural Performance** (arXiv) - **CUTEv2: Unified and Configurable Matrix Extension for Diverse CPU Architectures with Minimal Design Overhead** (arXiv) - **Codasip RISC-V sale fuels speculation GlobalFoundries could be expanding its processor ambitions - MSN** (google_riscv) - **Introduction to RISC-V Instruction Set Architecture - Astute Group** (google_arch) - **CacheMind turns chip tuning into a conversation, exposing hidden cache failures and lifting processor performance - Tech Xplore** (google_arch) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - notebookcheck.net** (google_arch) - **Microchip Upgrades Its Mi-V RV32 RISC-V Soft-Core Processor, Promises a Major Speed Boost - Hackster.io** (google_riscv) - **CPU Instruction Set Architecture (ISA) Market - Market Growth Reports** (google_arch) - **SystemRescue 13 lands with Linux 6.18 and bcachefs support** (the_register) - **Alibaba's New RISC-V CPU for AI: A Competitor to Apple & Arm Designs - News and Statistics - IndexBox** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch) - **AheadComputing Inc. Raises Additional $30M Seed2 Round to Reimagine CPU Architecture - Eastern Progress** (google_arch) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - theregister.com** (google_riscv) - **India Launches DHRUV64, Its First 1 GHz, 64-bit Dual-Core RISC-V CPU - TechPowerUp** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **A Precision Emulation Approach to the GPU Acceleration of Ab Initio Electronic Structure Calculations** (arXiv) - **Who Checks the Checker? Enhancing Component-level Architectural SEU Fault Tolerance for End-to-End SoC Protection** (arXiv) - **Nvidia's CUDA platform now supports RISC-V — support brings open source instruction set to AI platforms, joining x86 and Arm - Tom's Hardware** (google_riscv) - **China claims to have developed the world's first AI-designed processor — LLM turned performance requests into CPU architecture - Tom's Hardware** (google_arch) - **AheadComputing Inc. Raises Additional $30M Seed2 Round to Reimagine CPU Architecture - easternprogress.com** (google_arch) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Throughput Optimization as a Strategic Lever in Large-Scale AI Systems: Evidence from Dataloader and Memory Profiling Innovations** (arXiv) - **CXLRAMSim v1.0: System-Level Exploration of CXL Memory Expander Cards** (arXiv) - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv) - **One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon** (riscv_news) - **RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Highly-Parallel Atom-Detection Accelerator for Tweezer-Based Neutral Atom Quantum Computers** (arXiv) - **Physical Design of UET-RVMCU: A Streamlined Open-Source RISC-V Microcontroller** (arXiv) - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **Telink TL3228 – Low-power, low-latency dual-core RISC-V wireless MCU supports Bluetooth 6.0, 802.15.4, and 2.4 GHz proprietary - CNX Software** (google_riscv) - **RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual** (riscv_news) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Per-Bank Memory Bandwidth Regulation for Predictable and Performant Real-Time System** (arXiv) - **Toward a Universal GPU Instruction Set Architecture: A Cross-Vendor Analysis of Hardware-Invariant Computational Primitives in Parallel Processors** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **Support RAJA and Scientific Applications on RVV Architectures** (riscv_news) - **Breker Verification Systems and Frontgrade Gaisler Collaborate on High-Reliability RISC-V Fault Tolerant Processor Core - businesswire.com** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Current RISC-V CPUs Being Too Slow Causes Headaches For Fedora: ~5x Slower Builds - Phoronix** (google_riscv) - **AI is stress-testing processor architectures and RISC-V fits the moment - EDN - Voice of the Engineer** (google_riscv) - **SpacemiT to launch server-class RISC-V processor following capital injection - South China Morning Post** (google_riscv) - **Europe’s RISC-V processor developer up for sale ... - eeNews Europe** (google_riscv) - **MIPS expands RISC-V processor platform with ARC IP integration - digitimes** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **The RISC-V Vector Extensions for AI - jonpeddie.com** (google_riscv) - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - cnx-software.com** (google_riscv) - **TUMCREATE Leads Development of Open-Source Post-Quantum Secure RISC-V Processor - thequantuminsider.com** (google_riscv) - **Alibaba XuanTie C950 – A powerful, RVA23-complaint 64-bit RISC-V core for Edge AI computing - cnx-software.com** (google_riscv) - **Ubitium bets one RISC-V chip can clean up embedded computing’s processor sprawl - jonpeddie.com** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Vividnode Mobile AI Packs RISC-V Processor and 60 TOPS AI Engine - LinuxGizmos.com** (google_riscv) - **Security Researchers Find Current RISC-V CPU Implementations Coming Up Short - Phoronix** (google_riscv) - **Alibaba XuanTie C950 – A powerful, RVA23-complaint 64-bit RISC-V core for Edge AI computing - CNX Software** (google_riscv) - **The next RISC-V processor frontier: AI - EDN - Voice of the Engineer** (google_riscv) - **Ubitium bets one RISC-V chip can clean up embedded computing’s processor sprawl - Jon Peddie Research** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **TRINE: A Token-Aware, Runtime-Adaptive FPGA Inference Engine for Multimodal AI** (arXiv) - **2DIO: A Cache-Accurate Storage Microbenchmark** (arXiv) - **AMD's new desktop CPU oozes cache out of all 16 cores** (the_register) - **Most Read – Alibaba Risc-V CPU, Foundry revenues, Dancing robots - Electronics Weekly** (google_riscv) - **Ben C.'s Clever Compiler Imports Verilog Designs, Including a Working RISC-V CPU, Into Factorio - Hackster.io** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **TorR: Towards Brain-Inspired Task-Oriented Reasoning via Cache-Oriented Algorithm-Architecture Co-design** (arXiv) - **PRISM: Breaking the O(n) Memory Wall in Long-Context LLM Inference via O(1) Photonic Block Selection** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_riscv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **RISC-V Vector Extension: Between standardization and tailor-made accelerators - eeNews Europe** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **PAI: Fast, Accurate, and Full Benchmark Performance Projection with AI** (arXiv) - **TurboMem: High-Performance Lock-Free Memory Pool with Transparent Huge Page Auto-Merging for DPDK** (arXiv) - **Reliable performance with RISC-V: Why architecture, microarchitecture and compilers must work together - eeNews Europe** (google_riscv) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - techpowerup.com** (google_arch) - **India Launches DHRUV64, Its First 1 GHz, 64-bit Dual-Core RISC-V CPU - techpowerup.com** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **Alibaba delivers RISC-V server chip optimized to run China’s top AI models** (the_register) - **TUMCREATE to Develop Open-Source RISC-V Processor with Integrated Post-Quantum Security - Quantum Computing Report** (google_riscv) - **TUMCREATE Leads Development of Open-Source Post-Quantum Secure RISC-V Processor - The Quantum Insider** (google_riscv) - **Alibaba launches 5nm Risc-V CPU for inference - Electronics Weekly** (google_riscv) - **Alibaba unveils 'highest performing RISC-V CPU in the world' to power 'Agentic AI' - MSN** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **SpacemiT K3 "16-core" RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **160-core RISC V Board Is The M.2 CoProcessor You Didn’t Know You Needed - Hackaday** (google_riscv) - **Using a Performance Model to Implement a Superscalar CVA6** (riscv_news) - **Alibaba Reveals XuanTie C950 RISC-V Processor - Let's Data Science** (google_riscv) - **Alibaba launches 5nm RISC-V CPU for inference - Electronics Weekly** (google_riscv) --- *Sponsored by LimitLess AI*

## Episode Summary In this episode, we cover: - **As Alibaba launches server-grade RISC-V CPU, Beijing throws its weight behind ISA - theregister.com** (google_riscv) - **Breker Verification Systems and Frontgrade Gaisler Collaborate on High-Reliability RISC-V Fault Tolerant Processor Core - Business Wire** (google_riscv) - **Renesas Unveils the First Generation of Own 32-bit RISC-V CPU Core Ahead of Competition - Renesas Electronics** (google_riscv) - **MIPS Rolls Out Its First RISC-V Processor Core – It’s a Big ‘Un - EEJournal** (google_riscv) - **New RISC-V microprocessor can run CPU, GPU, and NPU workloads simultaneously - Tom's Hardware** (google_riscv) --- *Sponsored by LimitLess AI*