EPISODE · Nov 28, 2006
Design of CMOS Circuits in the Nanometer Regime: Leakage Tolerance
from [Audio] NCN Nanoelectronics: Tutorials · host Kaushik Roy
The scaling of technology has produced exponential growth in transistor development and computing power in the last few decades, but scaling still presents several challenges. These two lectures will cover device aware CMOS design to address power, reliability, and process variations in scaled technologies for different application domains: high-performance with power as constraint and ultra-low power with reasonable performance.
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Design of CMOS Circuits in the Nanometer Regime: Leakage Tolerance
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