Building, programming, and validating low-power heterogeneous multi-core image processors

from InvasIC Seminar: Vorträge im SFB/TRR 89 · host Dr. Menno Lindwer

This talk highlights challenges and contributions in worst-case execution time analysis for real-time system considering architectural changes over time and discusses future trends and open research problems.

Episode metadata supplied by the publisher feed · Published Mar 26, 2015

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Building, programming, and validating low-power heterogeneous multi-core image processors

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