Episodes
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A RISC-V Experience Report
A RISC-V Experience Report
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A RISC-V Experience Report
A RISC-V Experience Report
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Scalable Data Management on Modern Networks
As data processing evolves towards large scale, distributed platforms, the network will necessarily play a substantial role in achieving efficiency and performance. Modern high-speed networks such as InfiniBand, RoCE, or Omni-Path provide advanced features such as Remote-Direct-Memory-Access…
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Scalable Data Management on Modern Networks
As data processing evolves towards large scale, distributed platforms, the network will necessarily play a substantial role in achieving efficiency and performance. Modern high-speed networks such as InfiniBand, RoCE, or Omni-Path provide advanced features such as Remote-Direct-Memory-Access…
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Approximate Computing: Design & Test for Integrated Circuits
Approximate Computing: Design & Test for Integrated Circuits
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Approximate Computing: Design & Test for Integrated Circuits
Approximate Computing: Design & Test for Integrated Circuits
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AnyDSL: A Partial Evaluation Framework for Programming High-Performance Libraries
AnyDSL: A Partial Evaluation Framework for Programming High-Performance Libraries
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AnyDSL: A Partial Evaluation Framework for Programming High-Performance Libraries
AnyDSL: A Partial Evaluation Framework for Programming High-Performance Libraries
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Cross Media File Storage with Strata
Current hardware and application storage trends put immense pressure on the operating system's storage subsystem. On the hardware side, the market for storage devices has diversified to a multi-layer storage topology spanning multiple orders of magnitude in cost and performance. Applications...
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Cross Media File Storage with Strata
Current hardware and application storage trends put immense pressure on the operating system's storage subsystem. On the hardware side, the market for storage devices has diversified to a multi-layer storage topology spanning multiple orders of magnitude in cost and performance. Applications...
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Security in FPGA-Accelerated Clouds
Security in FPGA-Accelerated Clouds
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Security in FPGA-Accelerated Clouds
Security in FPGA-Accelerated Clouds
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Applying Model-Driven Engineering in the co-design of Real-Time Embedded Systems
The resources available on a chip such as transistors and memory, the level of integration and the speed of components have increased dramatically over the years. Even though the technologies have improved, we continue to apply outdated approaches to our use of these resources. Key computer…
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Applying Model-Driven Engineering in the co-design of Real-Time Embedded Systems
The resources available on a chip such as transistors and memory, the level of integration and the speed of components have increased dramatically over the years. Even though the technologies have improved, we continue to apply outdated approaches to our use of these resources. Key computer…
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Designing autonomic heterogeneous computing architectures: a vision
The resources available on a chip such as transistors and memory, the level of integration and the speed of components have increased dramatically over the years. Even though the technologies have improved, we continue to apply outdated approaches to our use of these resources. Key computer…
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Designing autonomic heterogeneous computing architectures: a vision
The resources available on a chip such as transistors and memory, the level of integration and the speed of components have increased dramatically over the years. Even though the technologies have improved, we continue to apply outdated approaches to our use of these resources. Key computer…
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Game-theoretic Semantics of Synchronous Reactions
The synchronous model of programming, which emerged in the 1980ies and has led to the development of well-known languages such as Statecharts, Esterel, Signal, Lustre, has made the programming of concurrent systems with deterministic and bounded reaction a routine exercise. However, validity of...
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Game-theoretic Semantics of Synchronous Reactions
The synchronous model of programming, which emerged in the 1980ies and has led to the development of well-known languages such as Statecharts, Esterel, Signal, Lustre, has made the programming of concurrent systems with deterministic and bounded reaction a routine exercise. However, validity of...
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Security Enhanced Multi-Processor System Architecture for Mixed-Critical Embedded Applications
Complex mixed-critical embedded applications integrate different functionalities to satisfy the performance requirements and take advantage of the available processing power of multi-core systems. The emerging so-called Internet-of- Things (IoT) requires these systems to be connected through the...
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Security Enhanced Multi-Processor System Architecture for Mixed-Critical Embedded Applications
Complex mixed-critical embedded applications integrate different functionalities to satisfy the performance requirements and take advantage of the available processing power of multi-core systems. The emerging so-called Internet-of- Things (IoT) requires these systems to be connected through the...
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From tamed heterogeneous cores to system wide intrusion tolerance
After having seen the transition from increasing processor speeds to increasing system-level parallelism and after realizing that energy, not the transistor budget is the limiting factor, a third trend is on the horizon and also already partially happening in todays CMOS systems, a transition…
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From tamed heterogeneous cores to system wide intrusion tolerance
After having seen the transition from increasing processor speeds to increasing system-level parallelism and after realizing that energy, not the transistor budget is the limiting factor, a third trend is on the horizon and also already partially happening in todays CMOS systems, a transition…
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High-Level Synthesis and Beyond
Ten year ago in SOCC’2006, my group presented xPilot – the high-level synthesis (HLS) tool developed at UCLA for automatic synthesis of behavior-level C/C++ specifications into highly optimized RTL code. In the same year, the startup company AutoESL was formed to commercialize our research on HLS…
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High-Level Synthesis and Beyond
Ten year ago in SOCC’2006, my group presented xPilot – the high-level synthesis (HLS) tool developed at UCLA for automatic synthesis of behavior-level C/C++ specifications into highly optimized RTL code. In the same year, the startup company AutoESL was formed to commercialize our research on HLS…
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Adaptive Parallel and Distributed Software Systems
Parallel and distributed systems are a pervasive component of the modern computing environment. Today, large-scale data-centers or supercomputing facilities have become ubiquitous, consisting of heterogeneous geo-distributed clusters with 100s of thousands of general-purpose multicores,...
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Adaptive Parallel and Distributed Software Systems
Parallel and distributed systems are a pervasive component of the modern computing environment. Today, large-scale data-centers or supercomputing facilities have become ubiquitous, consisting of heterogeneous geo-distributed clusters with 100s of thousands of general-purpose multicores,...
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Control-theoretic approaches to Energy Minimization under Soft Real-Time Constraints
Embedded real-time systems must meet timing constraints while minimizing energy consumption. To this end, many energy optimizations are introduced for specific platforms or specific applications. These solutions are not portable, however, and when the application or the platform change, these...
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Control-theoretic approaches to Energy Minimization under Soft Real-Time Constraints
Embedded real-time systems must meet timing constraints while minimizing energy consumption. To this end, many energy optimizations are introduced for specific platforms or specific applications. These solutions are not portable, however, and when the application or the platform change, these...
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Bytespresso, toward embedded domain-specific languages for supercomputing
As complex hardware architecture is widely adopted in high-performance computing (HPC), average HPC programmers are faced with serious difficulties in programming in a general-purpose language. Thus domain-specific languages (DSLs) are actively studied for HPC as a solution. DSLs are categorised...
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Bytespresso, toward embedded domain-specific languages for supercomputing
As complex hardware architecture is widely adopted in high-performance computing (HPC), average HPC programmers are faced with serious difficulties in programming in a general-purpose language. Thus domain-specific languages (DSLs) are actively studied for HPC as a solution. DSLs are categorised...
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Elastic Computing - Towards a New Paradigm for Distributed Systems
In this talk, which is based on our newest findings and experiences from research and industrial projects, I addressed one of the most relevant challenges for a decade to come: How to integrate the Internet of Things with software, people, and processes, considering modern Cloud Computing and...
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Elastic Computing - Towards a New Paradigm for Distributed Systems
In this talk, which is based on our newest findings and experiences from research and industrial projects, I addressed one of the most relevant challenges for a decade to come: How to integrate the Internet of Things with software, people, and processes, considering modern Cloud Computing and...
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Energy-Efficient Algorithms
We study algorithmic techniques for energy savings in computer systems. Research in this area concentrates mostly on two topics. (1) Power-down mechanisms: When a system is idle, it can be transitioned into low power stand-by or sleep states. The goal is to find state transition schedules that...
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Energy-Efficient Algorithms
We study algorithmic techniques for energy savings in computer systems. Research in this area concentrates mostly on two topics. (1) Power-down mechanisms: When a system is idle, it can be transitioned into low power stand-by or sleep states. The goal is to find state transition schedules that...
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Dataflow based Design and Implementation for Multicore Digital Signal Processors
In recent years, we have been seeing increased hardware and software support for dataflow programming incorporated into multicore digital signal processors (MDSPs) and their design environments. Key application areas for such technology include wireless communications, embedded computer vision…
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Dataflow based Design and Implementation for Multicore Digital Signal Processors
In recent years, we have been seeing increased hardware and software support for dataflow programming incorporated into multicore digital signal processors (MDSPs) and their design environments. Key application areas for such technology include wireless communications, embedded computer vision…
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Proof-Carrying Services
The vision of the Paderborn based cooperative research centre (CRC) 901, On-The-Fly Computing, is the nearly automatic configuration and execution of individualized IT services, which are constructed out of base services traded in world-wide available markets. In this talk, we first briefly...
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Proof-Carrying Services
The vision of the Paderborn based cooperative research centre (CRC) 901, On-The-Fly Computing, is the nearly automatic configuration and execution of individualized IT services, which are constructed out of base services traded in world-wide available markets. In this talk, we first briefly...
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Constructing Time-Predictable MPSoCs - Never Give up Control
Multi-core processors seem to be the solution to cope with the demand for more computational power that is foreseen for next-generation dependable embedded systems. Multicores promise to both outperform single-core processors and consume less energy than high-speed single cores of equivalent...
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Constructing Time-Predictable MPSoCs - Never Give up Control
Multi-core processors seem to be the solution to cope with the demand for more computational power that is foreseen for next-generation dependable embedded systems. Multicores promise to both outperform single-core processors and consume less energy than high-speed single cores of equivalent...
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Toward energy-neutral computational sensing - Challenges and opportunities
This talk highlights challenges and contributions in worst-case execution time analysis for real-time system considering architectural changes over time and discusses future trends and open research problems.
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Toward energy-neutral computational sensing - Challenges and opportunities
This talk highlights challenges and contributions in worst-case execution time analysis for real-time system considering architectural changes over time and discusses future trends and open research problems.
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Predictability for Uni- and Multi-Core Real-Time/Cyber-Physical Systems
This talk highlights challenges and contributions in worst-case execution time analysis for real-time system considering architectural changes over time and discusses future trends and open research problems.
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Building, programming, and validating low-power heterogeneous multi-core image processors
This talk highlights challenges and contributions in worst-case execution time analysis for real-time system considering architectural changes over time and discusses future trends and open research problems.
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Multi- and Many-Core Architectures - A Trip over a Bumpy Road
General purpose CPUs with dozens of computing cores are currently reaching the market. Some researchers even expect chips with thousands of computing cores to be available in the foreseeable future. In this talk we will discuss the architectures of some current multi- and many-core CPUs with an...
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Predictability for Uni- and Multi-Core Real-Time/Cyber-Physical Systems
This talk highlights challenges and contributions in worst-case execution time analysis for real-time system considering architectural changes over time and discusses future trends and open research problems.
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Multi- and Many-Core Architectures - A Trip over a Bumpy Road
General purpose CPUs with dozens of computing cores are currently reaching the market. Some researchers even expect chips with thousands of computing cores to be available in the foreseeable future. In this talk we will discuss the architectures of some current multi- and many-core CPUs with an...
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Building, programming, and validating low-power heterogeneous multi-core image processors
This talk highlights challenges and contributions in worst-case execution time analysis for real-time system considering architectural changes over time and discusses future trends and open research problems.
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Accelerating Data Processing Using FPGAs
Accelerating Data Processing Using FPGAs
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Accelerating Data Processing Using FPGAs
Accelerating Data Processing Using FPGAs