Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures

## Episode Summary In this episode, we cover: - **Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures** (arXiv) - **CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees** (arXiv) - **The key CPU architecture you've never heard of: RISC-V - Red Shark News** (google_arch) - **RISC-V Vector Extension: Between standardization and tailor-made accelerators - eeNews Europe** (google_riscv) - **A RISC-V vector extension primer - Adafruit** (google_riscv) --- *Sponsored by LimitLess AI*