Skip to content
Q&A#06- How can I generate a new clock from a reference clock? episode artwork

Mar 1, 2019 10 min

Q&A#06- How can I generate a new clock from a reference clock?

from Five Minute VHDL Podcast Hosted by Francesco Richichi

I receiver a question from Sandip. He got my reference, from my post on DDS. The question is: “I want to generate Square of 999kHz, 1000kHz and 1001kHzin VHDL Language and that would be implemented on a Zynq ZC702 evaluation board. Is it possible by using the DDS.? Can you provide your expertise and comment on it.” Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music by Francis Preve - https://www.francispreve.com

Episode details come from the podcast's RSS feed.

Embed this episode

Ready to play

Q&A#06- How can I generate a new clock from a reference clock?

0:00 10:37

No transcript yet.

Requests help us decide what to transcribe next.

Share this episode

Frequently asked questions

How long is this episode of Five Minute VHDL Podcast?

This episode is 10 minutes long.

When was this Five Minute VHDL Podcast episode published?

This episode was published on March 1, 2019.

Can I download this Five Minute VHDL Podcast episode?

Yes. Use the download control on the episode player to save the publisher-provided media file.