PODCAST · technology
Five Minute VHDL Podcast
by Francesco Richichi
Let's talk about hardware design using VHDL
Episodes
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Q&A#10 RAM Parallelism
How I can parallelize a RAM in FPGA https://surf-vhdl.com/how-to-implement-a-multi-port-memory-on-fpga/ Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses...
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ep#22-Multiplier optimization
Learn how to optimize a multiplier in particular cases: For a technical analysis go to the post: https://surf-vhdl.link/OptimizationVhdl12b25 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram…
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Ep#21-Serial-to-Parallel Parallel-to-Serial converter
Link to the post: https://surf-vhdl.link/99990 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music by Francis Preve -...
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Q&A#09-I need a clock!
In this podcast we will understand how to connect a clock signal to our FPGA Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses
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Q&A#08- What is the dithering
What is dithering? Where we can use this technique? Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music by Francis Preve -...
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ep#20-VHDL Generic
VHDL Generic Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music by Francis Preve - https://www.francispreve.com
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Ep#19-Iterative statement
Even if the VHDL is not a software language, we can find a tyoica SW statement, the iterative statement. Let’s see how to use this https://t.me/SurfVhdl/92 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram:...
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Ep#18-the conditional assignment in VHDL
Let’s understand how to implement a conditional statement in VHDL image for the episode http://t.me/SurfVhdl/86 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses...
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ep#17-wait
Wait Statements in VHDL Reference to pictures: https://t.me/SurfVhdl/82 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music by Francis...
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Q&A#07- What is the first thing that a recruiter does?
Q&A#07- What is the first thing that a recruiter does? When a recruiter needs to hire you as VHDL expert, what do you think he or she will do to understand if you are good for him or her? What can you do in order to result a VHDL user? Let’s see in this podcast. Here you can find the feedback of…
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Ep#16-VHDL process
And now is time to introduce formally a Process link to the images https://t.me/SurfVhdl/78 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses…
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Q&A#06- How can I generate a new clock from a reference clock?
I receiver a question from Sandip. He got my reference, from my post on DDS. The question is: “I want to generate Square of 999kHz, 1000kHz and 1001kHzin VHDL Language and that would be implemented on a Zynq ZC702 evaluation board. Is it possible by using the DDS.? Can you provide your expertise...
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Ep#15-VHDL Packages
VHDL Packages http://t.me/SurfVhdl/74 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music by Francis Preve - https://www.francispreve.com
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Ep#14-VHDL object
After signal introduction, let's view what are the remaining VHDL objects Images https://t.me/SurfVhdl/72 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses...
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Q&A#05- Does the USB transfer work as UART?
I received a question from Haitham. He have to connect a computer to an FPGA using USB connection in order to transfer data from FPGA to the PC. Haitham is following my VHDL course “Start Learning VHDL Using FPGA”. In this course the last LAB implement communication between PC and FPGA using UART...
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QA#04-What is the VHDL design flow
In this Q&A episode I want to answer to the question on what is the VHLD design flow To better follow the episode, see the picture on the telegram channel https://t.me/SurfVhdl/65 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected]...
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Ep#13-a way to remember-the flip-flop
Introducing Flip-Flop in VHDL Link to the picture in the telegram channel https://t.me/SurfVhdl/61 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses...
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QA#3-plzz send the test bench
This is the question many of you ask me very often I wish to give you some hint and a test bench template I use in my VHDL designs Here the link to the test bench template: https://t.me/SurfVhdl/58 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail:...
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Ep#12-VHDL Simulation
A brief overview to setup a ModelSim simulation environment Link to the episode#12 picture t.me/SurfVhdl/53 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses...
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Ep#11-what is a signal
Introduce signal in VHDL, what is a signal and how to use it. Image relative to this episode Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses…
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Ep#10-More on driver the resolution function
Solving a dispute in VHDL: the resolution function Link to image for the episode#10 Solving a dispute in VHDL: the resolution function t.me/SurfVhdl/50 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram:...
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Ep#09-What is a driver in VHDL
What is a driver in VHDL? Images for the episode t.me/SurfVhdl/46 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music by Francis Preve -...
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QA#2-SPI-controller-simulation with Vivado
In this brief episode I want to answer a question from Klajdi on simulation of SPI controller using Vivado Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses...
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QA#1-Do we need clock and address
Answering to Prashant. He asked me this question “What do we have to give as an input for i_clk and i_addr?” relative to the post: https://surf-vhdl.com/how-to-generate-sine-samples-in-vhdl/ Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail:...
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Ep#08-concurrency
In this episode we will introduce the Concurrency concept Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music by Francis Preve -...
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Ep#07-introducing the entity
Introducing Entity. The basic building VHDL block Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music by Francis Preve -...
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Ep#06-Ok, and now how do I test it?
Let’s understand how digital electronics help us in the debug and test of our design Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music...
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Ep#05-male and female logic
Learn how men and women can be identified as digital circuits Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music by Francis Preve -...
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EP#04-Two is enough
Why do we use only two logic level in digital design? Figures: https://t.me/SurfVhdl/32 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses...
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Ep#03-a really important thing the interfaces
Let's introduce the FLAT and Hierarchical methodology in Hardware Design Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music by Francis...
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Ep#02-the three secrets that no hardware designer will ever tell you
Start understanding few rules for a good VHDL design habits Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music by Francis Preve -...
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Ep#01-Why you should learn VHDL
Do you like digital electronic? Why you should learn VHDL? Let's understand in this episode Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses…
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Ep#0-why a podcast on VHDL
Episode zero to introduce the Surf-VHDL Podcast: Five Minute VHDL Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: [email protected] Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/couses Music by Francis Preve -...
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ABOUT THIS SHOW
Let's talk about hardware design using VHDL
HOSTED BY
Francesco Richichi
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How many episodes does Five Minute VHDL Podcast have?
Five Minute VHDL Podcast currently has 33 episodes available on PodParley. New episodes are automatically indexed when they're published to the podcast feed.
What is Five Minute VHDL Podcast about?
Let's talk about hardware design using VHDL
How often does Five Minute VHDL Podcast release new episodes?
Five Minute VHDL Podcast has 33 episodes. Check the episode list to see recent publication dates and frequency.
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Who hosts Five Minute VHDL Podcast?
Five Minute VHDL Podcast is created and hosted by Francesco Richichi.
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