Regular-Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures

## Episode Summary In this episode, we cover: - **Regular-Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures** (arXiv) - **Observation, Not Prediction: Conversation-Level Disaggregated Scheduling for Agentic Serving** (arXiv) - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual** (riscv_news) - **One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon** (riscv_news) --- *Sponsored by LimitLess AI*