SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network Accelerators through Co-Optimized Mapping and Scheduling

## Episode Summary In this episode, we cover: - **SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network Accelerators through Co-Optimized Mapping and Scheduling** (arXiv) - **Partitioned Tags, Shared Data: Reconciling Strict Cache Isolation with Write-Shared Coherence** (arXiv) - **Intel Panther Lake Technical Deep Dive - Compute Tile: CPU Architecture - TechPowerUp** (google_arch) - **Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core - CNX Software** (google_riscv) - **The next RISC-V processor frontier: AI - EDN - Voice of the Engineer** (google_riscv) --- *Sponsored by LimitLess AI*