Semi Doped

Vik Sekar and Austin Lyons tackle the biggest bottleneck in inference: moving data. They break down the three tiers of datacenter networking — scale up, scale out, scale across — and the core engineering trade-off at each layer: copper vs. optics. Topics include Nvidia's extreme measures to keep scale-up fabric electrical (a 78-layer mid-plane PCB), why Co-Packaged Optics is the "holy grail" everyone wants and no one can ship, and the serviceability problem standing in its way.Key Takeaways:A single 72-GPU scale-up rack needs 5,000+ cables spanning ~2 km — at that density, the power and cost of every connection becomes a system-level constraint, not an implementation detail.The scale-up rule is "copper when you can, optics when you must": each pluggable optical module adds ~30W, and with thousands of links in the fabric, that penalty compounds fast.Nvidia is pushing copper past its usual limits with a 78-layer mid-plane PCB — 3x+ the layer count of a typical complex board — specifically to avoid paying the optics power tax in its scale-up fabric.Scale-up isn't just a training problem. Frontier MoE models need 72-GPU domains to hit memory bandwidth targets, which pulls high-performance interconnect into the inference conversation.Scale-up has the highest connection density of the three tiers, making it the largest TAM and the sharpest three-way fight between NVLink, UA-Link, and Ethernet.Co-Packaged Optics could cut interconnect power by two-thirds — but a single failed laser could brick an entire multi-thousand-dollar GPU package, and that serviceability risk is what's keeping it on the roadmap instead of in racks.Chapters: 0:00 The Biggest Problem in Computing 7:14 The Three Tiers of Networking 13:49 Scale Up: Copper vs. Optics 17:59 Front-End vs. Back-End Networks 22:12 The Physical Scale of Cabling 28:46 Nvidia's 78-Layer Mid-Plane 33:16 How Optical Transceivers Work 39:16 The Power Penalty of Pluggables 42:09 The Business of Speed Transitions 44:40 The Promise and Peril of CPO 51:45 The Holy Grail of NetworkingFollow Chipstrat: Newsletter: https://www.chipstrat.com X: https://x.com/austinsemisFollow Vik: Newsletter: https://www.viksnewsletter.com/ X: https://x.com/vikramskrFollow Semi Doped: Get more of Austin and Vik daily, free: https://daily.semidoped.com/

Al Yuen, CEO of PicoJool, talks with Austin about using VCSELs for scale-up optical interconnects in AI data centers. Al explains why gallium arsenide (GaAs) supply is unconstrained while indium phosphide (InP) is limited, and how PicoJool can leverage existing supply chains to ship in the millions per month. They cover the roadmap from 1.6T to 12.8T, the trade-offs among 8×200G, 16×100G, and 32×50G, and the push to train the next generation of photonics engineers.The spec that changed is error rate. AI needs error-free links (10⁻¹⁰–10⁻¹² vs Ethernet's old 10⁻⁶) because GPUs act as one system — one error stalls the whole job.Single-mode optics can't hit the volume. Built for ~100K city-to-city links; datacenters need millions/month — a 10–50× gapGaAs vs InP is the whole supply story. VCSELs run on unconstrained GaAs; single-mode on constrained InP. 1M units: 8–10 weeks vs a sold-out 8–18 months.One platform, three flavors to 1.6T: 8×200G "fast and narrow," 16×100G LPO low-power, 32×50G NRZ "slow and wide" — pick on power, cost, and BER.12.8T needs no new tech — just more of the same: 64 channels (4×16 array in a finger-sized connector) × 200G, scaling channels, bi-di wavelengths, and lane speed.Capacity isn't the time consuming part — qualification is. WIN runs ~1,000 wafers/week at ~240K VCSELs each, so 1M units = ~10 wafers. The wait is tier-1 (>6 mo) and tier-2 (~3 mo) quals.Chapters:0:00 Meet Al Yuen and PicoJool2:29 Inventing the active optical cable5:03 Engineering mindset, copper limits8:43 Why VCSELs13:45 Scale-up and bit error rate20:09 Unconstrained vs constrained supply21:53 Indium phosphide bottleneck25:49 VCSEL design and foundry handoff31:59 Product road map, 200G launch34:16 Path to 3.2T and 12.8T40:10 Ordering a million VCSELs45:10 Ramp timing and training new engineersFollow Chipstrat:Newsletter: https://www.chipstrat.comX: https://x.com/chipstratFollow Vik:Newsletter: https://www.viksnewsletter.com/X: https://x.com/vikramskrFollow Semi Doped:Get more of Austin and Vik daily, free!Sign up: https://daily.semidoped.com/

Vik welcomes Val Bercovici from Weka to discuss the rapidly evolving landscape of AI memory and storage. Val explains how Weka's architecture leverages high-bandwidth networks to make storage faster than motherboard DRAM. They dive into KV cache optimizations, the future of NAND flash tiers, and the role of CXL in AI inference. The episode concludes with a look at predictive memory offloading and the AI flywheel.Chapters:0:00 Welcome Val Bercovici, Weka1:59 Memory situation and model routing3:50 KV cache offloading to CMX6:10 Network faster than motherboard13:10 Weka as AI memory infrastructure14:45 Inference market is different16:06 Memory hierarchy and KV cache19:40 KV cache optimizations and demand25:20 DeepSeek's cache read pricing34:49 NAND flash tiers: SLC vs QLC43:01 High Bandwidth Flash (HBF)49:59 CXL versus other interconnectsFollow Chipstrat:Newsletter: https://www.chipstrat.comX: https://x.com/chipstratFollow Vik:Newsletter: https://www.viksnewsletter.com/X: https://x.com/vikramskrFollow Semi Doped:Get more of Austin and Vik daily, free!Sign up: https://daily.semidoped.com/

Austin and Vik break down the current memory crisis, where AI demand is driving unprecedented profits for memory makers like Micron, while simultaneously causing inflation and price hikes for consumer electronics. They discuss how even premium brands like Apple are struggling to secure supply, leading them to controversial suppliers. The hosts also explore the long-term implications of AI's insatiable memory appetite and its impact on both data center and consumer markets.Chapters:0:00 Memory crisis hits1:20 AI impacting consumers3:00 AI causing inflation6:48 Consumer demand drop?8:49 AI demand inelastic10:56 Long-term memory outlook11:02 GoPro's memory woes12:24 Apple's pricing power18:20 Apple seeks CXMT DRAM21:38 Shrinkflation for phones23:16 Korea's memory investment26:10 Micron's killing profits33:00 Why AI needs so much DRAM40:27 Future of AI training44:34 Cost-optimizing inferenceFollow Chipstrat:Newsletter: https://www.chipstrat.comX: https://x.com/chipstratFollow Vik:Newsletter: https://www.viksnewsletter.com/X: https://x.com/vikramskrFollow Semi Doped:Get more of Austin and Vik daily, free!Sign up: https://www.semidoped.com/

Qualcomm flew Austin to New York for its investor day, where the communications company laid out a plan to make data center, automotive, and IoT two-thirds of its business by FY29. Austin was in the room and asked Cristiano Amon a question on the record. Vik watched the whole thing on YouTube. Together they break down what actually changed.The technical centerpiece is High Bandwidth Compute (HBC): stacking LPDDR on top of logic to expose the whole face of the chip for interconnects, claiming up to 100x more lanes and a path around the HBM bandwidth bottleneck. Austin and Vik dig into what's really under that memory, why "no advanced packaging needed" just moves the hard problem somewhere worse, and how it compares to d-Matrix. And as Austin put it: don't let anyone tell you HBM is dead. MOAR memory.Then the roadmap: the AI200/250/300 accelerators, the C1000 server CPU (5 GHz, 250+ cores, Meta as a customer), the Alphawave and Modular acquisitions, and Chris Lattner's Mojo.The most interesting takeaway might not be the data center at all. Qualcomm's edge play — AI-defined vehicles, cars as token generators, and a $1T robotics opportunity by 2040 — could be where High Bandwidth Compute matters most. Chapters: 0:00 Communications? That's just the start 4:08 Inside Qualcomm's investor day 9:16 Can Qualcomm build a data center business? 13:09 Disaggregated inference opens the door 17:57 High Bandwidth Compute: memory on the XPU 30:29 "No advanced packaging" just moves the problem 36:20 The roadmap, Alphawave, and Modular 46:00 The C1000 CPU and the agentic shortage 50:40 Cars as token generators, the $1T robotics bet 57:32 The memory market: MOARFollow Semi Doped: Get more of Austin and Vik daily, free! Sign up: https://www.semidoped.com/Connect with Vik and Austin: Vik's Paid Substack: https://www.viksnewsletter.com Austin's Paid Substack: https://www.chipstrat.com

New episode: Advanced packaging for AI chips, from wire bonds to TSMC CoWOS and Intel EMIB.Packaging is no longer an afterthought. It is the chip, and Intel's EMIB challenges TSMC's CoWOS.Three CoWOS flavors: silicon, organic RDL, local bridgesEMIB embeds tiny bridges into the substrate, no interposerEMIB-T and EMIB-M add through-silicon vias and power capacitorsGoogle is booking 3M TPUs on EMIB via MediaTek by 2028Package sizes keep climbing: 5.5x reticle today, 40x aheadThis episode is brought to you by SambaNova. Try SambaNova's fast inference today at the SambaNova Dashboard!Connect with Vik and Austin via a daily free newsletter:https://www.semidoped.comVik's Paid Substack: https://www.viksnewsletter.comAustin's Paid Substack: https://www.chipstrat.comChapters: (0:00) "There Is No Chip Without the Packaging" (0:28) Intro and SpaceX IPO Day (5:15) What We're Covering: CoWOS, EMIB, Google (7:40) Simple Packaging: Wire Bonds to Flip Chip (17:07) What Makes Packaging "Advanced" (33:44) CoWOS: Three Flavors Explained (45:30) EMIB: Intel's Embedded Bridge Approach (52:47) EMIB-T and EMIB-M (57:31) CoWOS vs. EMIB Trade-offs (1:02:18) Google's 3M TPU EMIB Order

Austin and Vik discuss their recent experience at Computex, where they met for the first time in person after six months of podcasting together. They share insights about the massive show, the people they connected with, and the exciting developments in AI hardware and interconnect technology. Connect with Vik and Austin via a daily free newsletter:https://www.semidoped.comVik's Paid Substack: https://www.viksnewsletter.comAustin's Paid Substack: https://www.chipstrat.comChapters00:00 Meeting in Person for the First Time03:05 Experiencing Computex: A Massive Show05:17 Connecting with the Audience: Real-Life Encounters06:46 Networking with Industry Leaders10:42 Keynote Highlights: Marvell's Vision15:11 The Future of Interconnects: CPO and Beyond22:54 Exploring Optical Interconnects and Future Technologies25:56 Micro LED Developments and Future Conferences27:34 Power Innovations in Data Centers30:54 Intel's Keynote and New CPU Technologies36:31 Intel Foundry's Advancements and Industry Implications

Huawei dropped a paper claiming 1.4nm-class performance without EUV, and the internet immediately declared ASML dead and US export controls useless. Austin and Vik recorded one day after Memorial Day to unpack what Huawei actually announced at ISCAS 2026 — and why the "EUV killer" headline gets the story backwards.They walk through the tau scaling law (tau is delay, and the idea is to attack it at the system level instead of the transistor), logic folding via hybrid bonding, the Kirin 2026 that doubles transistor count without shrinking, and who can actually manufacture stacked logic. Then the other tau knobs: a unified memory bus and near-packaged optics. Along the way: BESI vs EV Group, die-to-wafer vs wafer-to-wafer bonding, and why hybrid bonding isn't export-controlled the way EUV is.The takeaway is the opposite of the headline. Tau scaling is rational engineering under constraint, it's bullish for ASML (two DUV wafers per product, not fewer), and the moment EUV-enabled fabs stack their own advanced-node wafers, the gap widens instead of narrowing. Bullish advanced packaging, bullish EDA and multiphysics.Chapters:0:00 The "EUV killer" paper that broke the internet2:28 What Huawei actually announced at ISCAS4:00 Tau scaling: optimize delay, not transistors8:58 The equation and the 10x AI claim11:05 Logic folding: stacking logic on logic17:24 Who builds it, and can hybrid bonding be banned?24:16 Why this is bullish for ASML29:49 The other tau knobs: memory and optics35:18 Takeaways: packaging, EDA, multiphysicsFollow Semi Doped:Get more of Austin and Vik daily, free!Sign up: https://www.semidoped.com/Follow Chipstrat:Newsletter: https://www.chipstrat.comX: https://x.com/chipstratFollow Vik:Newsletter: https://www.viksnewsletter.comX: https://x.com/vikramskr

Spend one hour here and you've caught up on the entire arc of semiconductor lithography. Austin and Vik run a masterclass on the technology that decides who gets to make leading-edge chips, and why so few companies can afford to.The thread is economics. An EUV machine runs about $400 million, a new fab needs roughly 15 of them, and the total bill clears $20-30 billion before a single wafer ships. Austin and Vik trace the whole story: Rock's Law and the cost of a fab, what it actually takes to build one, the evolution from 193nm DUV through multi-patterning to 13.5nm EUV, how ASML generates EUV light by exploding falling tin droplets, and the move to high NA and its mirrors. Along the way, the fun history — i-line, krypton fluoride, immersion lithography, and the engineer who started it all by flipping a microscope upside down.Then the part that matters most: where lithography goes next. Two startups, xLight and Substrate, are attacking the cost problem from first principles. xLight wants to decouple the light source from the scanner with a free-electron laser and sell photons as a service. Substrate wants to skip EUV entirely and revive X-ray lithography. If either works, the economics of who can build a fab change completely.Chapters: 0:00 The 13F panic, and today's topic 2:23 Why the real story is economics, not physics 6:18 Austin in the clean room: graphene and bunny suits 10:06 Rock's Law and the $20 billion fab 18:08 DUV, the Sharpie, and a history of light 24:58 Multi-patterning, explained with a football field 34:45 How EUV makes 13.5nm light from tin droplets 41:14 High NA, anamorphic optics, and the half-field tax 46:45 The startups rethinking lithography: xLight and SubstrateRelevant reading: Chipstrat — The economics of lithography: https://www.chipstrat.com/p/lithography-economics Chipstrat — xLight and photons as a service: https://www.chipstrat.com/p/photons-as-a-service Chipstrat — Substrate and X-ray lithography: https://www.chipstrat.com/p/substrate Vik's Newsletter — the viability of X-ray lithography: https://www.viksnewsletter.com/p/an-in-depth-look-at-the-viability Fred Chen — LELE multipatterning and EUV stochastics (Substack): https://frederickchen.substack.com/p/can-lele-multipatterning-help-against Chip War, Chris Miller Focus, Marc Hijink (the ASML book): https://www.amazon.com/Focus-Inside-struggle-complex-machine-ebook/dp/B0CW1FLCD4Follow Chipstrat: Newsletter: https://www.chipstrat.com X: https://x.com/chipstratFollow Vik: Newsletter: https://www.viksnewsletter.com/ X: https://x.com/vikramskrFollow Semi Doped: Get more of Austin and Vik daily, free! Sign up: https://www.semidoped.com/

Cerebras IPO is the only thing to talk about this week. 🔥IPO prices at $185/share. Pops nearly 70% right after. The first wafer-scale chip company to make it public — after a 40-year curse killed every prior attempt.A water-cooler-style convo on what Cerebras actually builds, why a 23 kW wafer is a power and cooling nightmare, why 44 GB of SRAM is both the magic and the wall for LLM inference, and the cursed Trilogy Systems saga that Gene Amdahl tried — and failed — to pull off in 1983.Why does Cerebras leave the whole wafer intact instead of dicing it? How do they route around defects to harvest ~900K working cores out of ~1M? Why is power delivery vertical, and why does the wafer literally expand a tenth of a millimeter when it heats up? What does the OpenAI deal actually buy — wafers, or tokens? And why does that distinction matter?Chapters: 0:00 Cold open: 23 kW per wafer 0:15 Cerebras IPO day at $185 2:39 What's a wafer-scale engine 10:30 Power, cooling, and thermal expansion 18:12 The 44 GB wall 26:35 The Trilogy Systems curse 32:11 Supercomputing → training → inference 39:36 The OpenAI deal and the Wild WestRelevant reading: Vik's Substack post on the Cerebras IPO and OpenAI deal: https://www.viksnewsletter.com/Follow Chipstrat: Newsletter: https://www.chipstrat.com X: https://x.com/austinsemisFollow Vik: Newsletter: https://www.viksnewsletter.com/ X: https://x.com/vikramskrFollow Semi Doped: Get more of Austin and Vik daily, free! Sign up: https://www.semidoped.com/

Gimlet Labs runs an inference cloud built on heterogeneous silicon. Their software traces a PyTorch workload, segments it into its component parts, and schedules each piece onto the best-suited hardware — connecting chips from different vendors on a single high-speed fabric.In this interview, Gimlet co-founder Natalie Serrino and former Intel executive Beltir walk through the architecture (graph trace, optimal split points, lowering each segment to TensorRT on NVIDIA and equivalents elsewhere), the three customer segments they sell into (frontier labs, sovereign clouds, AI natives), and a concrete demo: on GPT-OSS 120B at 8K input / 1K output, running the speculative decoder on a d-Matrix Corsair card while NVIDIA B200s handle the verifier shifts the throughput-vs-interactivity Pareto frontier roughly 4× over GPU-only speculative decode.The most surprising takeaway: most Neoclouds gave significant equity to a single silicon vendor in exchange for capacity. Hardware amortization is around 70% of their annual costs, and the equity terms prevent them from diversifying their silicon. So the only software innovation they can ship is disaggregation on top of one vendor's stack — never across vendors. Gimlet's two-track model (deploying orchestration software inside customer data centers, plus running their own Neocloud built on mixed silicon) is the answer to that constraint.Read the full transcript on Chipstrat.Chapters:0:00 Intro and the chips no one's connected before0:33 Inference cloud for agents1:02 From Intel to Gimlet2:14 The case for heterogeneous inference4:03 Disaggregating inference by resource profile6:24 Tracing PyTorch into a schedulable graph8:08 Connecting chips never connected before10:52 CPUs as the agentic workhorse12:01 Tool calls in the same data center as the LLM13:21 Latency vs throughput on a shared fabric14:57 Three customer buckets15:54 Sovereigns: make an API call, not a porting project19:37 "Cracked software is the platform"22:24 Why merchant silicon vendors need partners25:18 Hyperscalers outsourcing CapEx, not just kernels28:49 AI natives: latency budgets, not just price32:06 The d-Matrix partnership33:31 The Pareto frontier chart35:56 Speculative decode on Corsair: 4× shift37:27 4× faster, or 3× more customers?41:22 Why most Neoclouds can't follow this model42:34 Gimlet's two-track business model44:30 CoreWeave vs Together vs Gimlet45:15 Series A and hiringRelevant reading:The Information on Gimlet helping OpenAI optimize for Cerebras: https://www.theinformation.com/newsletters/ai-agenda/startup-helping-openai-optimize-ai-cerebras-chipsSachin Katti and Zain Asgar coauthored research at Stanford: https://arxiv.org/abs/2507.19635Follow Chipstrat:Newsletter: https://www.chipstrat.comX: https://x.com/chipstrat

What's common to optics and power that ruins everything in the era of AI?Resistance.The same physics that drove interconnects to optics is now driving low-voltage power delivery up to 800V. Austin Lyons (Chipstrat) and Vik Sekar (Vik's Newsletter) unpack it using the Kyber rack as an example.At 600kW and 48V, you're pushing 12,500 amps through a single rack. Power loss scales with I². The math doesn't work. The fix is 800V — and the parts come straight from the EV traction inverter ecosystem (SiC, GaN, IGBTs).We cover the full grid-to-GPU power conversion chain (substation, utility room, PSU, intermediate bus converter, VRM), why vertical power delivery is the CPO equivalent for power, and why the power industry is a much wider open problem than optics or HBM. Plus the new topology fight: 800V → 48V (reuse the existing 48V infrastructure) vs 800V → 6V (skip 48V entirely, like TI and Navitas are pushing).We also touch Coherent's six-inch indium phosphide ramp at Järfälla, Sweden, and why margins are the real read-through next quarter.Relevant reading: Vik's Substack post on power: https://www.viksnewsletter.com/p/power-delivery-as-the-next-physics-wall Google TPU 8i / 8t blog (Boardfly deep dive): https://cloud.google.com/blog/products/compute/tpu-8t-and-tpu-8i-technical-deep-diveGet more of Austin and Vik daily, free! Sign up here: https://www.semidoped.com/Follow Chipstrat:Newsletter: https://www.chipstrat.comX: https://x.com/austinsemisFollow Vik:Newsletter: https://www.viksnewsletter.com/X: https://x.com/vikramskrChapters(00:00) Intro(01:41) Memory tax: inflation, not innovation(03:46) Boardfly: 16 hops to 7(05:12) Coherent's six-inch indium phosphide ramp(12:15) Power is the next physics wall(15:08) Why 48V breaks at 600kW: 12,500 amps(23:05) 800V and vertical power delivery: CPO for power(30:34) Grid to GPU: every stage is a different supply chain(39:20) 800V → 48V or skip straight to 6V?

The hyperscaler memory tax quarter.More CapEx? Pssh. We knew flops needed scaling.But $25B at Microsoft alone just to pay higher component prices? A memory tax. That's the news.NAND? Sold out. HBM? Sold out.What we cover:SanDisk revenue +97% sequential.78% gross margin. Guidance above 80% next quarter.Samsung HBM4 first to ship. Demand outstripping supply.DeepSeek v4 goes SSD-centric. KV cache offloads to flash.Microsoft: $25B of 2026 CapEx is just memory pricing.Jassy: memory shortage pushes on-prem to AWS.Qualcomm: mystery custom ASIC. Ships December.New Semi Doped with @vikramskr and @austinsemis.Check out our Substacks- https://www.viksnewsletter.com/ - https://www.chipstrat.com/Chapters:0:00 Intro and Vik goes full-time5:15 Earnings week: the memory tax7:26 Samsung HBM4 and the Gbps race14:42 Is the memory tax worth it?17:37 SanDisk and the SunDisk origin23:22 78% gross margins and 5-year supply lock-ins29:29 DeepSeek v4 and SSD-centric inference38:49 Hyperscaler CapEx and the cloud pull42:49 AI accelerators: TPU, Trainium, MTIA